Rate-compatible LDPC codes with short block lengths based on puncturing and extension techniques

Liu, Jingjing; Lamare, Rodrigo C. de

doi:10.1016/j.aeue.2015.07.008

Cited by 6 publications

(3 citation statements)

References 33 publications

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“…Compared to other error-correction codes, like Bose-Chaudhuri-Hocquenghem (BCH) codes, Reed Solomon (RS) codes, and turbo codes, LDPC codes have many advantages, e.g., very low error floor, high-speed encoder and decoder, and more varieties in code construction [20][21][22][23]. Therefore, LDPC codes have become the focal choice for many communication standards, such as 10-Gigabit Ethernet (802.3an) [24] and Wi-Fi (802.11n/ac/ad) [25][26][27].…”

Section: Introductionmentioning

confidence: 99%

Reduced‐Complexity LDPC Decoding for Next‐Generation IoT Networks

Asif

Khan

Afzal

et al. 2021

Wireless Communications and Mobile Computing

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Low-density parity-check (LDPC) codes have become the focal choice for next-generation Internet of things (IoT) networks. This correspondence proposes an efficient decoding algorithm, dual min-sum (DMS), to estimate the first two minima from a set of variable nodes for check-node update (CNU) operation of min-sum (MS) LDPC decoder. The proposed architecture entirely eliminates the large-sized multiplexing system of sorting-based architecture which results in a prominent decrement in hardware complexity and critical delay. Specifically, the DMS architecture eliminates a large number of comparators and multiplexors while keeping the critical delay equal to the most delay-efficient tree-based architecture. Based on experimental results, if the number of inputs is equal to 64, the proposed architecture saves 69%, 68%, and 52% area over the sorting-based, the tree-based, and the low-complexity tree-based architectures, respectively. Furthermore, the simulation results show that the proposed approach provides an excellent error-correction performance in terms of bit error rate (BER) and block error rate (BLER) over an additive white Gaussian noise (AWGN) channel.

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Section: Introductionmentioning

confidence: 99%

Reduced‐Complexity LDPC Decoding for Next‐Generation IoT Networks

Asif

Khan

Afzal

et al. 2021

Wireless Communications and Mobile Computing

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“…These codes possess a rateless Raptor code property as well as good error correction performance of MET-LDPC codes under a low SNR. The raptor-like structure is important for providing rate compatibility and obtaining capacity-approaching performance, particularly at low code rates [28,29]. The generator matrix of the Raptor codes is randomly generated; thus, it is impossible to remove all short cycles in the matrix, and the error correction performance is unstable.…”

Section: Introductionmentioning

confidence: 99%

Rate compatible reconciliation for continuous-variable quantum key distribution using Raptor-like LDPC codes

Zhou,

Wang,

Zhang

et al. 2021

Preprint

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In the practical continuous-variable quantum key distribution (CV-QKD) system, the postprocessing process, particularly the error correction part, significantly impacts the system performance. Multi-edge type low-density parity-check (MET-LDPC) codes are suitable for CV-QKD systems because of their Shannon-limit-approaching performance at a low signal-to-noise ratio (SNR). However, the process of designing a low-rate MET-LDPC code with good performance is extremely complicated. Thus, we introduce Raptor-like LDPC (RL-LDPC) codes into the CV-QKD system, exhibiting both the rate compatible property of the Raptor code and capacity-approaching performance of MET-LDPC codes. Moreover, this technique can significantly reduce the cost of constructing a new matrix. We design the RL-LDPC matrix with a code rate of 0.02 and easily and effectively adjust this rate from 0.016 to 0.034. Simulation results show that we can achieve more than 98% reconciliation efficiency in a range of code rate variation using only one RL-LDPC code that can support high-speed decoding with an SNR less than -16.45 dB. This code allows the system to maintain a high key extraction rate under various SNRs, paving the way for practical applications of CV-QKD systems with different transmission distances.

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“…These codes are used in type two Hybrid ARQ in which extra parity bits are sent by the transmitter only in case the decoder is unsuccessful in correcting the errors [14]. In the case of LDPC, depending on the structure of the extension in the PCM the code performance can be drastically enhanced [12,15]. For the new 5G standard, multiple new sets of PCMs are introduced [16].…”

Section: Introductionmentioning

confidence: 99%

CVR: A Continuously Variable Rate LDPC Decoder Using Parity Check Extension for Minimum Latency

Pourjabar

Choi

2020

J Sign Process Syst

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This brief presents a novel IEEE 802.16e (WiMAX) based decoder that performs close to the 5G code but without the expensive hardware re-development cost. The design uses an extension of the existing WiMAX parity check code to reduce the processing latency and power consumption while keeping the decoder throughput at maximum. It achieves similar Frame Error Rate (FER) compared to 5G (0.1dB off), and most notably the error curves trend down like 5G instead flooring. At FER= −3 10 there is 0.1 dB gain in the FER code performance compared to WiMAX. An implementation of the design is a modified version of the existing fully-parallel WiMAX decoder that supports multirate codeword size and reduces latency by 33%. Additionally, for SNR greater than 3dB, decoding only the shorter code reduces the power consumption by 36%.

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Rate-compatible LDPC codes with short block lengths based on puncturing and extension techniques

Cited by 6 publications

References 33 publications

Reduced‐Complexity LDPC Decoding for Next‐Generation IoT Networks

Reduced‐Complexity LDPC Decoding for Next‐Generation IoT Networks

Rate compatible reconciliation for continuous-variable quantum key distribution using Raptor-like LDPC codes

CVR: A Continuously Variable Rate LDPC Decoder Using Parity Check Extension for Minimum Latency

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