Abstract:Nanostructure gradients exhibiting graded variation in a nanostructure geometric variable carry high promise as tool for parallel and high-throughput optimization of a range of on-chip devices and functional interfaces. The capabilities to fabricate nanostructure gradients, with desired size and slope, while preserving scalability and operational flexibility is however limited. In this direction, we demonstrate a simple and flexible approach to prepare nanostructure gradients, subjecting a functionalized chip … Show more
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