RCLK-VJ network reduction with Hurwitz polynomial approximation

Qin, Zhanhai; Cheng, Chung‐Kuan

doi:10.1145/1119772.1119827

Cited by 12 publications

(9 citation statements)

References 22 publications

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“…This has been observed already when nodes are reduced one at a time in Y − ∆ transformation algorithm [14]. As a result, how to remove those common factors (de-cancellation) in the rational functions of a BB * u,v (s) and b B * u (s) in general becomes a key issue for the subcircuit reduction process.…”

Section: Subcircuit Reduction and Ddd Graphs 21 Subcircuit Reductionmentioning

confidence: 96%

“…It was shown that YDDD representation is more compact than sequence of expressions [9,20], which essentially represent the complexity of symbolic node-by-node Gaussian elimination process. Hence time complexity of our reduction is better than Y − ∆ reduction algorithm [14], which is based on Gaussian elimination.…”

Section: Cancellation Due To Multiplication For Cancellation Frommentioning

confidence: 96%

“…This idea has been explored by approximate Gaussian elimination for RC circuits [3], by direct truncation of the transfer function algorithm (DTT) [10] for tree-structured RLC circuits and an extended DTT method for non-tree structured RLC circuits [21]. Recently a topology based node-reduction method was proposed [14], in which nodes are reduced one at a time (topologically it is called Y -∆ transformation) and the generated admittance in the reduced network is represented as an order-reduced rational function of s. This method is equivalent to symbolic Gaussian elimination (s is the only symbol) but the reduction is done on circuit topologies only. The stability is enforced by Hurwitz polynomial approximation.…”

Section: Introductionmentioning

confidence: 99%

“…The new method performs the node reduction directly on the circuit matrices and hence it is general enough to reduce any linear circuits. Furthermore, instead of reducing one node at a time as done in [14]. The new method allows elimination of multiple nodes simultaneously.…”

Section: Introductionmentioning

confidence: 99%

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A general s-domain hierarchical network reduction algorithm

Tan

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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This paper presents an efficient method to reduce complexities of a linear network in s-domain. The new method works on circuit matrices directly and reduces the circuit complexities by eliminating subcircuits in a hierarchical way. The resulting admittances in the reduced networks are kept as rational functions of s with reduced order. Some theoretical results are characterized for the presence of common factors coming from the suppression of subcircuits. A novel common factor removal (de-cancellation) strategy based on a graph-based hierarchical subcircuit reduction process is proposed. The resulting reduction algorithm is applicable to any linear circuits in s-domain. The stability of the reduced system is enforced by applying the Hurwitz polynomial approximation. The reduced systems can be used for fast s-domain analysis and for time domain waveform evaluation. Experimental results on both linear analog circuits and RLC circuits, and comparison with SPICE in s-domain analysis are also provided.

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Section: Subcircuit Reduction and Ddd Graphs 21 Subcircuit Reductionmentioning

confidence: 96%

Section: Cancellation Due To Multiplication For Cancellation Frommentioning

confidence: 96%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A general s-domain hierarchical network reduction algorithm

Tan

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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“…Stable admittances and transfer functions can be obtained from £ admittances because of this nice property [14]. This further treatment is not in DTT.…”

Section: Generalized Formula For Y-£ Transformationmentioning

confidence: 99%

Realizable parasitic reduction using generalized Y-Δ transformation

Qin¹,

Cheng²

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)

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Abstract-We propose a realizable RCLK-in-RCLK-out parasitic reduction technique. The method employs generalized Y-¡ transformation. In our method, admittances are kept in their original rational forms of ¢ , and their orders are reduced by truncating high-order terms. Therefore reduced admittances match the low-order terms in exact admittances. First-order realization of admittances is guaranteed, and higher-order realization is achieved by template optimization using Geometric Programming. The algorithm uniquely uses common-factor identification and cancelation operations to make Y-¡ transformation numerically stable. The experiment shows that our method can achieve higher reduction ratio than TICER and comparable simulation results with PRIMA.

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Linear System of Order Reduction Using a Modified Balanced Truncation Method

Suman

Kumar

2021

Circuits Syst Signal Process

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RCLK-VJ network reduction with Hurwitz polynomial approximation

Cited by 12 publications

References 22 publications

A general s-domain hierarchical network reduction algorithm

A general s-domain hierarchical network reduction algorithm

Realizable parasitic reduction using generalized Y-Δ transformation

Linear System of Order Reduction Using a Modified Balanced Truncation Method

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