Proceedings of the 28th International Workshop on Vertex Detectors — PoS(Vertex2019) 2020
DOI: 10.22323/1.373.0021
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RD53 analog front-end processors for the ATLAS and CMS experiments at the High-Luminosity LHC

Abstract: This work discusses the design and the main results relevant to the characterization of analog front-end processors in view of their operation in the pixel detector readout chips of ATLAS and CMS at the High-Luminosity LHC. The front-end channels presented in this paper are part of RD53A, a large scale demonstrator designed in a 65 nm CMOS technology by the RD53 collaboration. The collaboration is now developing the full-sized readout chips for the actual experiments. Some details on the improvements implement… Show more

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Cited by 5 publications
(8 citation statements)
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“…Some of the tested assemblies were irradiated to a fluence of ~10 16 n eq /cm 2 . The improved version of this ROC is called RD53B-CMS (also called CROC) [15,16]. It is the CMS final version of the chip and has a linear front-end [15].…”
Section: Sensor Readout Chip and Modulesmentioning
confidence: 99%
See 1 more Smart Citation
“…Some of the tested assemblies were irradiated to a fluence of ~10 16 n eq /cm 2 . The improved version of this ROC is called RD53B-CMS (also called CROC) [15,16]. It is the CMS final version of the chip and has a linear front-end [15].…”
Section: Sensor Readout Chip and Modulesmentioning
confidence: 99%
“…The use of the deep sub-micron CMOS technology and an efficient power architecture with a low supply voltage (1.2 V) demands a significant current level of about 2 A per ROC. In the serial power distribution design [17,18], a group of pixel channels share digital resources for buffering, control, and data formatting. The modules are powered in about 500 serial chains of up to 12 modules each.…”
Section: Power Architecturementioning
confidence: 99%
“…The basic functionalities of the RD53A chip and each of the three AFEs were previously verified and reported [22][23][24][25][26]. The objective of this work was to evaluate the three AFE designs against the CMS requirements, in terms of spurious hit rate, dead time, and radiation tolerance and to compare their performance.…”
Section: Trimmingmentioning
confidence: 99%
“…A significant improvement in time walk at the cost of a marginal increase in static current consumption was achieved by removing those two transistors. This led to a simpler TIA stage in the new design of the LIN AFE [31], for the next version of the chip, called RD53B [18].…”
Section: Lin Afe Slow Time Response Mitigationmentioning
confidence: 99%
“…Three analog front-end designs with different architectures have been realized [17]. All were proven to satisfy the requirements of RD53A, working at thresholds of about 1,200 e − with a noise occupancy at 10 −6 level, a time-walk smaller than 25 ns and a charge deposition measurement with Time-of-Threshold (ToT) technique.…”
Section: Vertex Detectorsmentioning
confidence: 99%