2007 Proceedings 57th Electronic Components and Technology Conference 2007
DOI: 10.1109/ectc.2007.373864
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Reaction Engineering of Through-Chip Via Filling for Wafer-Level 3D Packaging

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Cited by 4 publications
(2 citation statements)
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“…Therefore, it is necessary to develop a new Cu-via electrodeposition mechanism and chemistries due to its high aspect ratio and depth. For Cu electrodeposition in the TSV, the depth of the via is comparable to the thickness of a diffusion boundary layer [9]. It is very challenging and important to improve mass transport and the concentration gradient of reactants within the via to avoid via void or seam [8,10].…”
Section: Introductionmentioning
confidence: 99%
“…Therefore, it is necessary to develop a new Cu-via electrodeposition mechanism and chemistries due to its high aspect ratio and depth. For Cu electrodeposition in the TSV, the depth of the via is comparable to the thickness of a diffusion boundary layer [9]. It is very challenging and important to improve mass transport and the concentration gradient of reactants within the via to avoid via void or seam [8,10].…”
Section: Introductionmentioning
confidence: 99%
“…[12][13][14] The filling of blind holes with copper can be achieved by either dc or pulsereverse current wave forms. An oxygen purge performed during via filling is beneficial for the filling of blind holes with high aspect ratios ͑Ͼ10͒ using a pulse-reverse wave form, 15 and no leveling agents are needed.…”
mentioning
confidence: 99%