Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery

Abstract

Abstract-NAND flash memory reliability continues to degrade as the memory is scaled down and more bits are programmed per cell. A key contributor to this reduced reliability is read disturb, where a read to one row of cells impacts the threshold voltages of unread flash cells in different rows of the same block. Such disturbances may shift the threshold voltages of these unread cells to different logical states than originally programmed, leading to read errors that hurt endurance.For the first time in open literature, this paper experimentally characterizes read disturb errors on state-of-the-art 2Y-nm (i.e., 20-24 nm) MLC NAND flash memory chips. Our findings (1) correlate the magnitude of threshold voltage shifts with read operation counts, (2) demonstrate how program/erase cycle count and retention age affect the read-disturb-induced error rate, and (3) identify that lowering pass-through voltage levels reduces the impact of read disturb and extend flash lifetime. Particularly, we find that the probability of read disturb errors increases with both higher wear-out and higher pass-through voltage levels.We leverage these findings to develop two new techniques. The first technique mitigates read disturb errors by dynamically tuning the pass-through voltage on a per-block basis. Using real workload traces, our evaluations show that this technique increases flash memory endurance by an average of 21%. The second technique recovers from previously-uncorrectable flash errors by identifying and probabilistically correcting cells susceptible to read disturb errors. Our evaluations show that this recovery technique reduces the raw bit error rate by 36%.

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

“…Typical RD characteristics are reported in Figure 30 [255]: the V T shift is larger for the erased state and decreases for higher programmed V T levels, in agreement with the reduction on the tunnel oxide field. As a consequence, more errors are expected in the logical pages corresponding to those states.…”

“…Data for the V T shift as a function of the number of reads feature different dependences [255,256], while raw bit-error rate (RBER) data vs. the number of reads reveal a linear dependence whose slope increases with cycles [60,255,257], with a higher BER observed on SLCs than on MLCs. As with SILC, several process optimization [258,259], voltage tuning [255,260] or system-level correction [261] proposals have been put forward to alleviate the issue.…”

Error Analysis and Adaptable Error-correct Scheme for NAND Flash Memory

“…As the reading cycles increasing, the threshold voltage distribution of cells shifts to the right according to the results of [7]. Y. Cai [7] also indicates that the bit error rate increases roughly linearly with the number of read operations, and the read disturb effects are greater at high P/E cycles.…”

A page lifetime-aware scrubbing scheme for improving reliability of Flash-based SSD

“…The influence of read disturb is distinguishable after millions of read operations [13]. Thus the read disturb test did not perform independently.…”