READ:Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution

Han, Hyunseung; Chung, Jaeyong; Yang, Joon-Sung

doi:10.1109/tc.2018.2801856

Cited by 4 publications

(5 citation statements)

References 32 publications

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“…Additionally, high temperature is another source of transient errors, and the stacked architecture causes a heating problem since the lower layers of memory are less exposed to the heat dissipation, making them warmer more than the upper layers; thus, the heat profile in 3D memory provides different degrees of reliability for each layer. From a heat perspective, this makes the lower dies more susceptible to errors, forming an unequal distribution of SER through the 3D layers [13] [18].…”

Section: Soft Error Rate Analysis On 3d Memoriesmentioning

confidence: 99%

“…Han, Chung, and Yang [13] used both the effect of radiation and heat to produce a model of equations to estimate SER among the layer levels of a 3D-IC. Figure 1 depicts four test cases created by the authors using these equations: (a) SER of the uppermost layer is 10× higher than the other layers.…”

Section: Soft Error Rate Analysis On 3d Memoriesmentioning

confidence: 99%

“…Finally, we describe three works that analyze ECCs targeting 3D memories. Han, Chung, and Yang [13] proposed a novel ECC organization scheme for 3D memories to secure reliable operations under SER profiles. The proposed scheme does not require additional redundant arrays.…”

Section: State-of-the-artmentioning

confidence: 99%

“…Heat is another source of transient errors, and the heat profile in 3D memory provides varying degrees of reliability for each layer. From a heat perspective, the upper dies are less susceptible to errors, forming a different SER distribution in 3D memory [13]. Besides, the performance benefits and thermal impact of the stacked 3D microarchitecture have been studied recently, but the reliability implications and the MBU patterns when using 3D technology have received little attention.…”

Section: Introductionmentioning

confidence: 99%

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LPC: An Error Correction Code for Mitigating Faults in 3D Memories

Freitas

Mota

Marcon

et al. 2021

IEEE Trans. Comput.

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The radiation sensitivity of memory cells increases dramatically as CMOS manufacture technology scales down; therefore, the reliability of memories has become a challenge. 3D technology has gained attention for having several advantages compared to the 2D counterpart, such as high integration density, high performance, low power, and high communication speed. Although several studies are targeting 3D memories, the effects on reliability using this technology have received little attention. This work introduces Line Product Code (LPC), a modified product code-based Error Correction Code (ECC) that uses both Hamming and parity in both rows and columns to implement reliable 3D memories. We implemented two lightweight LPC-based decoding algorithms in interleaved (LPCa-I) and non-interleaved (LPCa) versions, which allowed us to analyze LPC through a set of simulation cases that considers four severity levels of error incidence. The experimental results showed the effectiveness of the LPC-based algorithms, reaching correction rates of up 2.3 times higher compared to other Hamming-based algorithms.

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Section: Soft Error Rate Analysis On 3d Memoriesmentioning

confidence: 99%

Section: Soft Error Rate Analysis On 3d Memoriesmentioning

confidence: 99%

Section: State-of-the-artmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

LPC: An Error Correction Code for Mitigating Faults in 3D Memories

Freitas

Mota

Marcon

et al. 2021

IEEE Trans. Comput.

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“…[3] It is also because of the broad application prospects of 3D-IC in the aerospace field, its irradiation effect has also received the researcher's attention. [4][5][6][7][8][9][10][11] Zhang et al made the first significant attempt to characterize the microarchitecture soft error vulnerabilities across the stacked chip layers under 3D integration technologies. [4] They showcased that alpha particles induced by package material only affect the top layers of the 3D-IC because the outer layers have a shielding effect on inner layers.…”

Section: Introductionmentioning

confidence: 99%

Geant4 simulation of proton-induced single event upset in three-dimensional die-stacked SRAM device*

Liu³

et al. 2020

Chinese Phys. B

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Geant4 Monte Carlo simulation results of the single event upset (SEU) induced by protons with energy ranging from 0.3 MeV to 1 GeV are reported. The SEU cross section for planar and three-dimensional (3D) die-stacked SRAM are calculated. The results show that the SEU cross sections of the planar device and the 3D device are different from each other under low energy proton direct ionization mechanism, but almost the same for the high energy proton. Besides, the multi-bit upset (MBU) ratio and pattern are presented and analyzed. The results indicate that the MBU ratio of the 3D die-stacked device is higher than that of the planar device, and the MBU patterns are more complicated. Finally, the on-orbit upset rate for the 3D die-stacked device and the planar device are calculated by SPACE RADIATION software. The calculation results indicate that no matter what the orbital parameters and shielding conditions are, the on-orbit upset rate of planar device is higher than that of 3D die-stacked device.

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