Readiness of the ATLAS Tile Calorimeter link daughterboard for the High Luminosity LHC era

Santurio, E. Valdes; Silverstein, S. B.; Böhm, C.

doi:10.22323/1.370.0087

Cited by 5 publications

(4 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The new structure divides the super-drawer into four independently powered and read-out mini-drawers (MDs) that are each half the length of the present drawer. Each mini-drawer, shown in figure 3 (left) houses up to 12 PMTs equipped with the front-end amplifier/shaper cards, a MainBoard [9] for control and digitalization, a DaughterBoard [10] for high speed communication and a high voltage distribution board. Each module with 4 (LB) or 3 (EB) mini-drawers has one low voltage power supply box, from where 10 V power is delivered to each half of the mini-drawer.…”

Section: Atlas Tile Demonstrator Modulementioning

confidence: 99%

Integration and commissioning of the ATLAS Tile Demonstrator Module for Run 3

Tlou

2022

J. Inst.

View full text Add to dashboard Cite

The electronics of the Tile Calorimeter at the ATLAS experiment will be replaced for the HL-LHC. The TileCal Phase-II upgrade project has undertaken an extensive R&D program. A Demonstrator module containing the upgraded on-detector readout electronics was built in 2014, evaluated in seven test beam campaigns, and inserted into one of the Tile Calorimeter modules at the ATLAS experiment in 2019. The module also provides backward compatibility of the Demonstrator module with the present ATLAS systems. We present the current status and test results from the Demonstrator module currently running at ATLAS.

show abstract

Section: Atlas Tile Demonstrator Modulementioning

confidence: 99%

Integration and commissioning of the ATLAS Tile Demonstrator Module for Run 3

Tlou

2022

J. Inst.

View full text Add to dashboard Cite

show abstract

“…The Daughter Board sends precision data as well as the slow control and monitoring data from the on-detector electronics. The Daughter Board receives the LHC clock and distributes it to the on-detector electronics and exchanges configuration and sends control commands to the front-end boards [15]. Each Daughter Board uses 2 Kintex Ultrascale FPGAs.…”

Section: Daughter Boardmentioning

confidence: 99%

Upgrade of ATLAS Hadronic Tile Calorimeter for the High-Luminosity LHC

Starovoitov¹

2022

Instruments

View full text Add to dashboard Cite

The Tile Calorimeter (TileCal) is a sampling hadronic calorimeter covering the central region of the ATLAS experiment, with steel as the absorber and plastic scintillators as the active medium. The High-Luminosity phase of the LHC, delivering five times the LHC’s nominal instantaneous luminosity, is expected to begin in 2029. TileCal will require new electronics to meet the requirements of a 1 MHz trigger, higher ambient radiation, and to ensure better performance under high pile-up conditions. Both the on- and off-detector TileCal electronics will be replaced during the shut-down of 2026–2028. The photomultiplier tube (PMT) signals from every TileCal cell will be digitized and sent directly to the back-end electronics, where the signals are reconstructed, stored, and sent to the first level of the trigger at a rate of 40 MHz. This will provide better precision in the calorimeter signals used by the trigger system and will allow the development of more complex trigger algorithms. The modular front-end electronics feature radiation-tolerant, commercial, off-the-shelf components and a redundant design to maintain system performance in case of single points of failure. The timing, control, and communication interface with the off-detector electronics is implemented with modern Field-Programmable Gate Arrays (FPGAs) and high-speed fiber optic links running up to 9.6 Gb/s. The TileCal upgrade program has included extensive R&D and test beam studies. A Demonstrator module with reverse compatibility with respect to the existing system was inserted in ATLAS in August 2019 for testing in actual detector conditions. The ongoing developments for on- and off-detector systems, together with expected performance characteristics and results of test-beam campaigns with the electronics prototypes, will be discussed.

show abstract

“…As observed in Figure 12, the phase noise values of all the e-link clocks exceeds the phase noise limits for the reference clocks addressed by the FPGA manufacturer. However, stable communication between the CPM and the Daughterboard v5 [16] is achieved using the GBT protocol at 4.8 Gbps for the downlink and 9.6 Gbps for the uplink.…”

Section: Clock Qualification Testsmentioning

confidence: 99%

Design of the Compact Processing Module for the ATLAS Tile Calorimeter

Carrió

2021

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

The LHC will undergo a major upgrade starting in 2025 towards the High Luminosity LHC (HL-LHC) to increase the instantaneous luminosity by a factor of 5 to 7 compared to the nominal value.The Phase-II Upgrade (2025-2027) will require the trigger and readout electronics of the ATLAS experiment to operate with the stringent conditions imposed by the HL-LHC. During this upgrade, both on-and off-detector readout electronics of TileCal will be completely replaced with a new data acquisition which will provide full-granularity information to the ATLAS trigger system.The Compact Processing Modules are responsible for the LHC bunch-crossing clock distribution towards the detector, configuration of the on-detector electronics, data acquisition, cell energy reconstruction, and data transmission to the TDAQ interface (TDAQi).The CPM has been designed as an AMC form-factor board equipped with 8 Samtec FireFly modules for communication with the detector, a Xilinx Kintex UltraScale FPGA for data acquisition and processing, a Xilinx Artix 7 FPGA for slow control and monitoring, and other subsystems to generate highquality clocks for the FPGAs and communications.The high-speed communication with the on-detector electronics is implemented via 32 GigaBit Transceiver links receiving detector data at 9.6 Gbps and transmitting commands and the LHC clock at 4.8 Gbps, while the reconstructed cell energies are transmitted to TDAQi via 4 FULL-mode links. Triggered data is transmitted through a FULL-mode link to the ATLAS TDAQ system via the FELIX network.This paper introduces the design of the Compact Processing Modules for the ATLAS Tile Calorimeter Phase-II Upgrade and the results and experiences with the first prototypes.

show abstract

Readiness of the ATLAS Tile Calorimeter link daughterboard for the High Luminosity LHC era

Cited by 5 publications

References 3 publications

Integration and commissioning of the ATLAS Tile Demonstrator Module for Run 3

Integration and commissioning of the ATLAS Tile Demonstrator Module for Run 3

Upgrade of ATLAS Hadronic Tile Calorimeter for the High-Luminosity LHC

Design of the Compact Processing Module for the ATLAS Tile Calorimeter

Contact Info

Product

Resources

About