Readout Firmware of the Vertex Locator for LHCb Run 3 and Beyond

Hennessy, K.; Prieto, A. Fernández; Regueiro, P. Vázquez; Buytaert, J.; Beuzekom, M. van; Cid, E. Lemos; Eklund, L.; Bruyn, K. De; Naik, Sneha; Schiller, M.; Murray, D.; Leflat, A.; Bassi, G.; Punzi, G.; Lazzari, F.; Morello, M. J.; García, O. Boente; Torreira, A. Gallas; Plana, B. Garcia; Bowcock, T. J. V.; Dettori, F.; Dreimanis, K.; Lima, V. Franco; Hutchcroft, D.; Shears, T.; Augusto, Oscar; Coco, V.; Collins, P.; Ferro‐Luzzi, M.; Schindler, H.; Akiba, K. Carvalho; Occo, Elena Dall'; Graz, Cristina Sanchez; Hulsbergen, W.; Hynds, D.; Kostiuk, I.; Merk, M.; Snoch, A.; Bobulska, D.; Capua, S. De; Dutta, D.; Gersabeck, M.; Parkes, C.; Švihra, Peter; Williams, Mark Richard James; Bogdanova, G. A.; Volkov, V.; Kopciewicz, P.; Majewski, M. W.; Obłąkowska-Mucha, A.; Rachwal, Bartlomej; Szumlak, T.; Garcia, L. Meyer; Marinho, F.; Mendes, Larissa Helena; Nasteva, I.; Otalora, Juan; Rodrigues, Gabriel Dias; Velthuis, J. J.; Jałocha, P.; John, M.; Jurik, N.; Scantlebury-Smead, Luke; Back, J. J.; Gershon, T.; Latham, T.; Morris, A. G.

doi:10.1109/tns.2021.3085018

Cited by 3 publications

(5 citation statements)

References 6 publications

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“…The firmware, described in detail in ref. [56], processes the data in the following way. First it performs the descrambling of the GWT serialiser output frame, splitting it back into the SPP format that was encoded on the VeloPix.…”

Section: Firmwarementioning

confidence: 99%

The LHCb Upgrade I

Aaij,

Abdelmotteleb,

Abellan Beteta

et al. 2024

J. Inst.

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The LHCb upgrade represents a major change of the experiment. The detectors have been almost completely renewed to allow running at an instantaneous luminosity five times larger than that of the previous running periods. Readout of all detectors into an all-software trigger is central to the new design, facilitating the reconstruction of events at the maximum LHC interaction rate, and their selection in real time. The experiment's tracking system has been completely upgraded with a new pixel vertex detector, a silicon tracker upstream of the dipole magnet and three scintillating fibre tracking stations downstream of the magnet. The whole photon detection system of the RICH detectors has been renewed and the readout electronics of the calorimeter and muon systems have been fully overhauled. The first stage of the all-software trigger is implemented on a GPU farm. The output of the trigger provides a combination of totally reconstructed physics objects, such as tracks and vertices, ready for final analysis, and of entire events which need further offline reprocessing. This scheme required a complete revision of the computing model and rewriting of the experiment's software.

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Section: Firmwarementioning

confidence: 99%

The LHCb Upgrade I

Aaij,

Abdelmotteleb,

Abellan Beteta

et al. 2024

J. Inst.

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“…SPs are output by the detector without a well-defined time ordering, and data from different LHC beam crossings (separated by 25 ns) may not be synchronized and mixed over time. The first step of the VELO data-processing firmware reorders the SPs, making sure that SPs coming from the same proton bunch crossing (event) are grouped together [8], before data are sent to the clustering stage. Reconstructed clusters are then formatted into LHCb event fragments and sent to the PCIe bus.…”

Section: Format and Features Of Velo Datamentioning

confidence: 99%

“…Fig. 2 shows a schematic view of the firmware [8] of the custom PCIe cards (TELL40 [9]) that perform the readout of the VELO. TELL40 cards are used as readout units for each subdetector Fig.…”

Section: Format and Features Of Velo Datamentioning

confidence: 99%

“…Each VELO TELL40 receives data from a single VELO module. Two independent and identical parallel processing chains are implemented in the FPGAs, each of which receives and processes data from one VELO half-module [8]. The clustering architecture, with all the needed ancillary logic, is integrated as a self-contained block at the end of each chain, and it has, therefore, two identical instances running in parallel, in analogy with the readout firmware (Fig.…”

Section: Implementation Details and Integrationmentioning

confidence: 99%

See 1 more Smart Citation

A FPGA-Based Architecture for Real-Time Cluster Finding in the LHCb Silicon Pixel Detector

Bassi

Giambastiani

Hennessy

et al. 2023

IEEE Trans. Nucl. Sci.

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This article describes a custom [very high speed integrated circuits (VHSIC) hardware description language (VHDL)] firmware implementation of a 2-D cluster-finder architecture for reconstructing hit positions in the new vertex pixel detector that is part of the large hadron collider beauty (LHCb) Upgrade. This firmware has been deployed to the existing field-programmable gate-array (FPGA) cards that perform the readout of the VErtex LOcator detector (VELO), as a further enhancement of the data-acquisition (DAQ) system, and will run in real-time during physics data taking, reconstructing VELO hits coordinates on-the-fly at the LHC collision rate. This preprocessing allows the first level of the software trigger to accept an 11% higher rate of events, as the ready-made hit coordinates accelerate the track reconstruction and consume significantly less electrical power. It additionally allows the raw pixel data to be dropped at the readout level, thus saving approximately 14% of the DAQ bandwidth. Detailed simulation studies have shown that the use of this real-time cluster-finding does not introduce any appreciable degradation in the tracking performance in comparison to a full-fledged software implementation. This work is part of a wider effort aimed at boosting the real-time processing capability of HEP experiments by delegating intensive tasks to dedicated computing accelerators deployed at the earliest stages of the data acquisition chain.

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“…The DAQ controls the hybrid (SOL40) and acquires and processes the data (TELL40) using a FPGA [4,5]. The SOL40 system uses the LHCb standard protocol (GBT) to communicate with the GBTx ASIC while the TELL40 system uses the VELO specific protocol (GWT) to receive data from the VeloPix ASIC at 5 Gb/s for a total of 20 readout links per module.…”

Section: Daq and Fpga Clusteringmentioning

confidence: 99%

Status of the LHCb Pixel Detector

Cid¹

2023

Proceedings of 10th International Workshop on Semiconductor Pixel Detectors for Particles and Imaging — PoS(Pixel2022)

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The LHCb experiment at CERN is a general-purpose forward spectrometer at LHC (CERN) optimized for heavy flavour physics and rare decays. It provides a coverage of 2 < 𝜂 < 5 with a momentum resolution of 0.5 % at pT < 20 GeV. A data-set of 10 fb −1 has been collected at the end of Run 2, followed by a major detector upgrade (Upgrade I), fully replacing the vertex and trigger subsystems [1]. The Vertex Locator (VELO) is a silicon pixel tracking detector in the heart of the LHCb spectrometer. As a higher instantaneous luminosity of 2 * 10 33 𝑠 −1 𝑐𝑚 −2 is expected during Run 3 (2022 -2025), the VELO has been upgraded by a brand-new detector. This new VELO replaces the silicon-strip technology with new 55 micrometers pitch pixels, operating as close as a 5 mm radius from the LHC beams. The VELO new readout ASIC, called VeloPix, is capable of operating at the 40 MHz collision rate, reaching 900 MHits/s. The detector is built with a modular design, composed of 52 modules divided into two-detector halves. The production of the required modules was completed in 2021, leading to the detector assembly phase. Both detector halves were successfully installed in May 2022. In this paper, the final steps of construction and installation will be shown. The detector is now under commissioning with beam and preliminary results will also be presented.

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Readout Firmware of the Vertex Locator for LHCb Run 3 and Beyond

Cited by 3 publications

References 6 publications

The LHCb Upgrade I

The LHCb Upgrade I

A FPGA-Based Architecture for Real-Time Cluster Finding in the LHCb Silicon Pixel Detector

Status of the LHCb Pixel Detector

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