Real area-power-delay trade-off in EUCLID logic synthesis system

Simultaneous gate sizing and placement

“…We calculate a fan-out induced DVCR of g i directly: (13) Notice that in equation (13), s l is calculated as the minimum slack time of any non-critical output of g i . figure 6, the dotted rectangle is the move DVCR of g 2 , which is the intersection of (11) applied to non-critical fan-in gates g 5 and g 6 and (13) applied to non-critical fan-out gates g 7 .…”

“…Although the number of variables and constraints maybe large, this is not a major concern since a Linear Programming problem can be solved very efficiently. We use LP-Solver of [13] to solve (16). Notice however that to improve the runtime of the LP solver, problem formulation (16) can be approximated by using a similar transformation to that which was used to obtain problem formulation (9) from problem formulation (8).…”

Concurrent logic restructuring and placement for timing closure

“…Gate sizing has been discussed extensively in literature [3][7] [8]. The work in [7] uses a discrete sizing model which is often too expensive to use even after the circuit is partitioned into smaller parts.…”

“…The work in [7] uses a discrete sizing model which is often too expensive to use even after the circuit is partitioned into smaller parts. The authors in [3][8] use continuous sizing methods, and formulate the sizing problem as a mathematical programming problem. In these works, the authors only adjust the gate sizes to match the output loads of the gates.…”

Cost, power, and parallelism in speech signal processing

“…Berkelaar and Theeuwen [19] provide a tool that directly manipulates designs to explore the area-power-delay space. In both of these approaches, however, since they do not consider supply voltage among the parameters under the control of the designer, some of their conclusions do not apply when supply voltage is jointly optimized with architecture.…”