Real Number Modeling of a SAR ADC behavior using SystemVerilog

Sapsanis, Christos; Villemur, Martin; Andreou, Andreas G.

doi:10.1109/smacd55068.2022.9816309

Cited by 3 publications

(2 citation statements)

References 7 publications

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“…A finite state machine (FSM) is a mathematical model used to represent systems that exhibit distinct states and transition between them based on inputs. It consists of a finite number of states, transitions, and events [4]. The different states depict the phases through which the ADC moves when it is required to convert data.…”

Section: B Finite State Machine Designmentioning

confidence: 99%

ADC Emulation on FPGA

Tabassum,

Prathik BV,

Hiremath

2022

International Journal of Electronics and Telecommunications

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Analog-to-Digital Converters (ADCs) are devices that transform analog signals into digital signals and are used in various applications such as audio recording, data acquisition, and measurement systems [1]. Prior to the development of actual chip, there is a need for prototyping, testing and verifying the performance of ADCs in different scenarios. Analog macros cannot be tested on an FPGA. In order to ensure the macros function properly, the emulation of the ADC is done first. This is a digital module and can be designed in System Verilog. This paper demonstrates the design of the module on FPGA for Analog to Digital Converter (ADC) emulation. The emulation is done specific to the ADC macro which has programmable resolutions of 12/10/8/6 bit.

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Section: B Finite State Machine Designmentioning

confidence: 99%

ADC Emulation on FPGA

Tabassum,

Prathik BV,

Hiremath

2022

International Journal of Electronics and Telecommunications

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“…The associate editor coordinating the review of this manuscript and approving it for publication was Yue Zhang . a signal flow-based modelling approach [3], [4], [5]. This means that every output of an analog component is sampled, in a discrete manner, from the inputs and the internal states.…”

Section: Introductionmentioning

confidence: 99%

Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator

Maurice,

Dessouky,

Salem

2023

IEEE Access

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Real Number Modelling (RNM) has become more common as a part of mixed-signal SoC validation. The paper illustrates modelling Phase Locked Loops (PLL) using SystemVerilog-Real Number Modelling (SV-RNM) as it's one of the essential blocks in any Integrated Circuit (IC) and a feedback loop system. It uses the Piece-Wise Linear (PWL) technique to model the loop filter with higher orders, higher than a first-order Low Pass Filter (LPF). The PWL technique needs both the value and the slope information so that the values between the samples can be interpolated, this is represented by the User-Defined Type (UDT) and Net (UDN). A fractional divider is modelled using the Sigma-Delta modulator of the Multi-stAge noiSe sHaping (MASH) 1-1-1 topology to generate the fractional part. Modelling non-linear effect like the phase noise of each sub-block, which is converted to the Root Mean Square (RMS)-jitter, by using the 'class' datatype that takes complex variables of real and imaginary values then returns some functionalities on these complex variables. Moreover, taking the loading effect due to capacitances and resistances at the output by using the User-Defined Resolved Nets (UDRN). The simulation results ensure that there is an accuracy improvement in the expected PLL outputs compared to the outputs from the transistor level with a much faster simulation time as an event-driven simulator is used.INDEX TERMS Real number modeling (RNM), SystemVerilog (SV), user-defined types (UDT), userdefined resolved nets (UDRN), phase locked loops (PLL), fractional dividers, piece-wise linear (PWL), phase noise (PN), RMS jitter, hardware description and verification language (HDVL).

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