Real-time adaptation of mobile antenna impedance matching

Boyle, Kevin; Bakker, T.; Jongh, M. de; Bezooijen, A. van

doi:10.1109/lapc.2010.5666808

Cited by 3 publications

(2 citation statements)

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“…As a further precaution, initial duplexer calibration can be run at less than maximum TX power to guarantee the power level at the RX side is sufficiently low so as not to cause any reliability issues. Further variations in antenna impedance are mainly due to human interaction and that makes it inherently slow; antenna tuners and the tracking loop should be able to cope with these changes and maintain a small signal at the LNA inputs [10], [12], [28]. Fig.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…In the on state, the transistor is in triode and can be modeled by its drain-source on resistance, as shown in Fig. 8(b), given by (10) where is the electron mobility, is the gate-oxide capacitance per unit area, and are the width and length of the transistor, and and are the gate-source and threshold voltage, respectively.…”

Section: Quality Factor and Tuning Range Tradeoffmentioning

confidence: 99%

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Tunable CMOS Integrated Duplexer With Antenna Impedance Tracking and High Isolation in the Transmit and Receive Bands

Abdelhalem

Gudem

Larson

2014

IEEE Trans. Microwave Theory Techn.

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A hybrid transformer-based integrated tunable duplexer is demonstrated. High isolation between the transmit and receive ports is achieved through electrical balance between the antenna and balance network impedances. A novel high-power-tolerant balance network, which can be tuned at both the transmit and receive frequencies, allows high isolation in both the transmit and receive bands even under realistic antenna impedance frequency dependence. To maintain high isolation despite antenna impedance variation, a feedback loop is employed to measure the transmitter leakage and correct the impedance of the balance network. An isolation 50 dB in the transmit and receive bands with an antenna voltage standing-wave ratio within 2:1 was achieved. The duplexer, along with a cascaded direct-conversion receiver, achieves a noise figure of 5.3 dB, a conversion gain of 45 dB, and consumes 51 mW of power. The insertion loss in the transmit path was less than 3.8 dB. Implemented in a 65-nm CMOS process, the chip occupies an active area of 2.2 mm .

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Section: Measurement Resultsmentioning

confidence: 99%

Section: Quality Factor and Tuning Range Tradeoffmentioning

confidence: 99%