IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society 2013
DOI: 10.1109/iecon.2013.6699492
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Real-time adjustment of power management policy for a time-based power control architecture

Abstract: As state-of-the-art mobile devices are demanded for high performance and attractive designs, system-on-chips have been integrated with many functional blocks into a single chip to reduce the chip size, cost, and power consumption. In this paper, to reduce power consumption of heterogeneous processor, a power management algorithm is proposed with a time-based power control architecture which autonomously performs voltage/clock scaling operations without the intervention of the processors. The proposed algorithm… Show more

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Cited by 3 publications
(2 citation statements)
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“…Whenever the environment fluctuates, it is difficult to set an optimal value, that is, to minimize the power consumption while maintaining the performance. Therefore, to track the optimal threshold value for variable input condition while keeping time constraints, the APM uses real-time control algorithms [4], [5].…”
Section: Application Processor Integrated With Modem Processormentioning
confidence: 99%
“…Whenever the environment fluctuates, it is difficult to set an optimal value, that is, to minimize the power consumption while maintaining the performance. Therefore, to track the optimal threshold value for variable input condition while keeping time constraints, the APM uses real-time control algorithms [4], [5].…”
Section: Application Processor Integrated With Modem Processormentioning
confidence: 99%
“…If the modem processor requests read/write operations when the memory interface blocks are off, the power control block turns on the memory interface blocks. The read/write operations are kept for certain duration in the power control block until the memory interface blocks are completely on [1,2]. Since the operation frequency of a modem and an AP differs, an asynchronous bridge block controls the clocks in the shared memory architecture.…”
Section: Dynamic Power/clock Gating In Shared Memory Interfacementioning
confidence: 99%