Real-time area efficient and high speed architecture design of Viterbi decoder

Middya, Amitava; Dhar, Anindya Sundar

doi:10.1109/aeeicb.2016.7538282

Cited by 5 publications

(2 citation statements)

References 6 publications

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“…The BMU calculates the Hamming distance between the received frame and the branch word while the PMU performs add-compare-select calculations as described in (Middya and Dhar, 2016). Figures 5 and 6 show the blocks used for the Hamming distance calculation and the ACS (add-compare-select) units.…”

Section: Branch Metric and Path Metric Unitsmentioning

confidence: 99%

Peer Review #4 of "A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study (v0.2)"

2020

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Integrated circuits may be vulnerable to hardware Trojan attacks during its design or fabrication phases. This paper is a case study of the design of a Viterbi decoder and the effect of hardware Trojans on a coded communication system employing the Viterbi decoder. Design of a Viterbi decoder and possible hardware Trojan models for the same are proposed. An FPGA-based implementation of the decoder and the associated Trojan circuits have been discussed. The noise-added encoded input data stream is stored in the block RAM of the FPGA and the decoded data stream is monitored on the PC through an UART interface. The implementation results show that there is barely any change in the LUTs used (0.5%) and power dissipation (3%) due to the insertion of the proposed Trojan circuits, thus establishing the surreptitious nature of the Trojan. In spite of the fact that the Trojans cause negligible changes in the circuit parameters, there are significant changes in the bit error rate (BER) due to the presence of Trojans. In the absence of Trojans, BER drops down to zero for SNRs higher than 6 dB, but with the presence of Trojans, BER doesn't reduce to zero even at a very high SNRs. This is true even with the Trojan being activated only once during the entire duration of the transmission.

show abstract

Section: Branch Metric and Path Metric Unitsmentioning

confidence: 99%

Peer Review #4 of "A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study (v0.2)"

2020

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show abstract

“…The BMU calculates the Hamming distance between the received frame and the branch word while the PMU performs add-compare-select (ACS) calculations as described in Middya & Dhar (2016). Figures 8 and 9 show the blocks used for the Hamming distance calculation and the ACS units.…”

Section: Branch Metric and Path Metric Unitsmentioning

confidence: 99%

A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study

Kakkara

Balasubramanian

Yamuna

et al. 2020

PeerJ Computer Science

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Integrated circuits may be vulnerable to hardware Trojan attacks during its design or fabrication phases. This article is a case study of the design of a Viterbi decoder and the effect of hardware Trojans on a coded communication system employing the Viterbi decoder. Design of a Viterbi decoder and possible hardware Trojan models for the same are proposed. An FPGA-based implementation of the decoder and the associated Trojan circuits have been discussed. The noise-added encoded input data stream is stored in the block RAM of the FPGA and the decoded data stream is monitored on the PC through an universal asynchronous receiver transmitter interface. The implementation results show that there is barely any change in the LUTs used (0.5%) and power dissipation (3%) due to the insertion of the proposed Trojan circuits, thus establishing the surreptitious nature of the Trojan. In spite of the fact that the Trojans cause negligible changes in the circuit parameters, there are significant changes in the bit error rate (BER) due to the presence of Trojans. In the absence of Trojans, BER drops down to zero for signal to noise rations (SNRs) higher than 6 dB, but with the presence of Trojans, BER doesn’t reduce to zero even at a very high SNRs. This is true even with the Trojan being activated only once during the entire duration of the transmission.

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Power and area optimized adaptive Viterbi decoder for high speed communication applications

Namratha

Bakhar

2022

Int. j. inf. tecnol.

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Real-time area efficient and high speed architecture design of Viterbi decoder

Cited by 5 publications

References 6 publications

Peer Review #4 of "A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study (v0.2)"

Peer Review #4 of "A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study (v0.2)"

A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study

Power and area optimized adaptive Viterbi decoder for high speed communication applications

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