Real-Time Control of I/O COTS Peripherals for Embedded Systems

Abstract

Real-time embedded systems are increasingly being built using commercial-off-the-shelf (COTS) components such as mass-produced peripherals and buses to reduce costs, timeto-market, and increase performance. Unfortunately, COTS interconnect systems do not usually guarantee timeliness, and might experience severe timing degradation in the presence of high-bandwidth I/O peripherals. To address this problem, we designed a real-time I/O management system comprised of 1) real-time bridges, and 2) a reservation controller. The proposed framework is used to transparently put the I/O subsystem of a COTS-based embedded system under the discipline of real-time scheduling. We also discuss computing a delay bound for I/O data transactions and determining worst-case buffer size. Finally, we demonstrate experimentally that our prototype real-time I/O management system successfully prioritizes I/O traffic and guarantees its timeliness.

A Predictable Execution Model for COTS-Based Embedded Systems

“…We assume that all data transfers target main memory, that is, data is always transferred between the peripheral's internal buffers and main memory. Therefore, we can treat main memory as a single resource shared by all peripherals and by the cache controller 1 . The CPU executes a set of N real-time periodic tasks Γ = {τ 1 , .…”

“…Since a highperformance COTS NIC is designed to autonomously transfer incoming packets to main memory as soon as possible, the NIC could potentially require memory access for significantly longer than its expected periodic reservation. In [1], [2], we introduced a solution to this problem consisting of a realtime I/O management scheme. A diagram of our proposed architecture is depicted in Figure 1.…”

“…Outgoing traffic is also retrieved from main memory in a predictable fashion. Bounds on the necessary buffer sizes so that data loss is avoided can be computed [1]. Our implemented real-time bridges are fully compatible with the PCIe standard and require no modification to either the system chipset or the controlled peripherals.…”

“…To address this problem, we expand upon on our previous work [1] and introduce hardware to put the I/O subsystem under the discipline of real-time scheduling.…”

“…In particular, predicting a precise pattern of cache fetches in main memory is very difficult, forcing the designer to make very pessimistic assumptions when performing schedulability analysis. To address this problem, PREM uses a novel program execution model with three main features: (1) jobs are divided into a sequence of non-preemptive scheduling intervals; (2) some of these scheduling intervals (named predictable intervals) are executed predictably and without cache-misses by prefetching all required data at the beginning of the interval itself; (3) the execution time of predictable intervals is kept constant by monitoring CPU time counters at run-time.…”