Reliable real-time low-latency spike sorting with large data throughput is essential for studies of neural network dynamics and for brain-machine interfaces (BMIs), in which the stimulation of neural networks is based on the networks' most recent activity. However, the majority of existing multi-electrode spike-sorting algorithms are unsuited for processing high quantities of simultaneously recorded data. Recording from large neuronal networks using large high-density electrode sets (thousands of electrodes) imposes high demands on the data-processing hardware regarding computational complexity and data transmission bandwidth; this, in turn, entails demanding requirements in terms of chip area, memory resources and processing latency. This paper presents computational complexity optimization techniques, which facilitate the use of spike-sorting algorithms in large multi-electrode-based recording systems. The techniques are then applied to a previously published algorithm, on its own, unsuited for large electrode set recordings. Further, a real-time low-latency high-performance VLSI hardware architecture of the modified algorithm is presented, featuring a folded structure capable of processing the activity of hundreds of neurons simultaneously. The hardware is reconfigurable "on-the-fly" and adaptable to the nonstationarities of neuronal recordings. By transmitting exclusively spike time stamps and/or spike waveforms, its real-time processing offers the possibility of data bandwidth and data storage reduction.
Index TermsFPGA; high throughput; low latency; multi-electrode; real-time; spike sorting
I IntroductionSignals in neuronal networks propagate as short fluctuations of the cell membrane potential -action potentials, which can be recorded extracellularly in the form of voltage spikes. The extraction of single-neuron activity from the recordings ("spike sorting") consists of a Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/ publications/rights/index.html for more information. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
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Europe PMC Funders Author ManuscriptsEurope PMC Funders Author Manuscripts number of nontrivial and error-prone processing steps, including spike detection, spike alignment, feature extraction and clustering [1].It has been shown that recording the electrical activity of a single neuron on multiple electrodes strongly increases spike-sorting performance [2]. In recent years, the advances in CMOS technology have led to the development of high-density multi-electrode arrays (HDMEAs) consisting of thousands of electrodes [3]- [6]. Applications of devices capable of recording single neuron activity on multiple electrodes range from in vivo studies of brain structure and clinical treatments to in vitro investigations of neural network dynamics, [7]- [9].High-density multi-electrode (HDME) neuronal recording systems t...