Real Time Hardware Accelerator for Image Filtering

Abstract

The image processing nowadays is a field in development, many image filtering algorithms are tested every day; however, the main hurdles to overcome are the difficulty of implementation or the time response in a general purpose processors. When the amount of data is too big, a specific hardware accelerator is required because a software implementation or a generic processor is not fast enough to respond in real time. In this paper optimal hardware implementation is proposed for extracting edges and noise reduction of an image in real time. Furthermore, the hardware configuration is flexible with the ability to select between power and area optimization or speed and performance. The results of algorithms implementation are reported.

High Throughput Spatial Convolution Filters on FPGAs

“…Their proposed filter architecture is tailored to a fixed set of coefficients and a fixed range of input values using the Bachet weight decomposition theorem. Ortega-Cisneros et al [30] present a 3×3 filter with fixed coefficients obtaining at best 318-MHz frequency. The work in [18] presents a multiplierless, coefficient independent filter that also utilizes a mechanism for zero padding at the borders.…”