Real-time hardware/software co-design of a traffic sign recognition system using Zynq FPGA

Farhat, Wajdi; Faiedh, Hassène; Souani, Chokri; Besbes, Kamel

doi:10.1109/idt.2016.7843059

Cited by 8 publications

(5 citation statements)

References 10 publications

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“…We use Xilinx Zynq-7020 FPGA [45] as our terminal device and Xilinx VU9P [46] as our edge server and prove the feasibility and efficiency of Cogent through design experiments. Table 1 shows our experimental configuration on both platforms and the resources available to them.…”

Section: Methodsmentioning

confidence: 99%

Collaborative Intelligence: Accelerating Deep Neural Network Inference via Device-Edge Synergy

Shan

Cui

2020

Security and Communication Networks

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With the development of mobile edge computing (MEC), more and more intelligent services and applications based on deep neural networks are deployed on mobile devices to meet the diverse and personalized needs of users. Unfortunately, deploying and inferencing deep learning models on resource-constrained devices are challenging. The traditional cloud-based method usually runs the deep learning model on the cloud server. Since a large amount of input data needs to be transmitted to the server through WAN, it will cause a large service latency. This is unacceptable for most current latency-sensitive and computation-intensive applications. In this paper, we propose Cogent, an execution framework that accelerates deep neural network inference through device-edge synergy. In the Cogent framework, it is divided into two operation stages, including the automatic pruning and partition stage and the containerized deployment stage. Cogent uses reinforcement learning (RL) to automatically predict pruning and partition strategies based on feedback from the hardware configuration and system conditions so that the pruned and partitioned model can better adapt to the system environment and user hardware configuration. Then through containerized deployment to the device and the edge server to accelerate model inference, experiments show that the learning-based hardware-aware automatic pruning and partition scheme can significantly reduce the service latency, and it accelerates the overall model inference process while maintaining accuracy. Using this method can accelerate up to 8.89× without loss of accuracy of more than 7%.

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Section: Methodsmentioning

confidence: 99%

Collaborative Intelligence: Accelerating Deep Neural Network Inference via Device-Edge Synergy

Shan

Cui

2020

Security and Communication Networks

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“…The described in the literature hardware implementations of traffic sign recognition mainly focus on solutions without the use of deep convolutional neural networks. In [7] and [8] the authors propose a software-hardware implementation of traffic sign detection based on colour information in the HSV space and pattern matching based classification. Article [9] describes a software-hardware solution based on the HOG (Histogram of Oriented Gradients) algorithm.…”

Section: Previous Workmentioning

confidence: 99%

Exploration of Hardware Acceleration Methods for an XNOR Traffic Signs Classifier

Przewłocka-Rus¹,

Kowalczyk²,

Kryjak³

2021

Preprint

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Deep learning algorithms are a key component of many state-of-the-art vision systems, especially as Convolutional Neural Networks (CNN) outperform most solutions in the sense of accuracy. To apply such algorithms in real-time applications, one has to address the challenges of memory and computational complexity. To deal with the first issue, we use networks with reduced precision, specifically a binary neural network (also known as XNOR). To satisfy the computational requirements, we propose to use highly parallel and low-power FPGA devices. In this work, we explore the possibility of accelerating XNOR networks for traffic sign classification. The trained binary networks are implemented on the ZCU 104 development board, equipped with a Zynq UltraScale+ MPSoC device using two different approaches. Firstly, we propose a custom HDL accelerator for XNOR networks, which enables the inference with almost 450 fps. Even better results are obtained with the second method - the Xilinx FINN accelerator - enabling to process input images with around 550 frame rate. Both approaches provide over 96% accuracy on the test set.

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“…The ARM is based on a serial operating mechanism and is responsible for the control of the laser, the energy monitoring of the pulses, data storage, and data transmission. The system adopts a software and hardware collaborative design approach [26], which integrates multi-channel data acquisition and lidar system control functions on a 115 mm × 141 mm circuit board, making the stability of the lidar system further improved.…”

Section: Introductionmentioning

confidence: 99%

An Integrated Off-Line Echo Signal Acquisition System Implemented in SoC-FPGA for High Repetition Rate Lidar

Cheng

Xie

2023

Electronics

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High repetition rate lidar is typically equipped with a low-energy, high repetition rate laser, and small aperture telescopes. Therefore, it is small, compact, low-cost, and can be networked for observation. However, its data acquisition and control functions are generally not specially designed, and the data acquisition, storage, and control programs need to be implemented on an IPC (Industrial Personal Computer), which increases the complexity and instability of the lidar system. Therefore, this paper designs an integrated off-line echo signal acquisition system (IOESAS) for lidar developed based on SoC FPGA (System-On-Chip Field Programmable Gate Array). Using a hardware–software co-design approach, the system is implemented in a heterogeneous multi-core chip ZYNQ-7020 (integrated FPGA and ARM). The FPGA implements dual-channel echo data acquisition (gated counting and hardware accumulation). At the same time, the ARM performs laser control and monitoring, laser pointing control, pulse energy monitoring, data storage, and wireless transmission. Offline data acquisition and control software was developed based on LabVIEW, which can remotely control the status of the lidar and download the echo data stored in IOESAS. To verify the performance of the data acquisition system, IOESAS was compared with the photon counting card P7882 and MCS-PCI, respectively. The test results show that they are in good agreement; the linear correlation coefficients were 0.99967 and 0.99884, respectively. IOESAS was installed on lidar outdoors for continuous detection, and the system was able to work independently and stably in different weather conditions, and control functions were tested normally. The gating delay and gating width time jitter error are ±5 ns and ±2 ns, respectively. The IOESAS is now used in several small lidars for networked observations.

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Real-time hardware/software co-design of a traffic sign recognition system using Zynq FPGA

Cited by 8 publications

References 10 publications

Collaborative Intelligence: Accelerating Deep Neural Network Inference via Device-Edge Synergy

Collaborative Intelligence: Accelerating Deep Neural Network Inference via Device-Edge Synergy

Exploration of Hardware Acceleration Methods for an XNOR Traffic Signs Classifier

An Integrated Off-Line Echo Signal Acquisition System Implemented in SoC-FPGA for High Repetition Rate Lidar

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