Real-time NURBS interpolation using FPGA for high speed motion control

FPGA-based hardware CNC interpolator of Bezier, splines, B-splines and NURBS curves for industrial applications

“…The pth-degree B-spline basis function is recursively defined as (5) and (6) for i = 0, 1,. . ., n (Yau et al, 2006).…”

“…Besides, for the B-spline and NURBS interpolators, Yau et al (2006) employed the Cox-de Boor algorithm for the online application. Notice that these works make the implementation of only one technique.…”

“…Also, there are several DSP developments for parametric interpolators and CNC controllers, being B-splines (Erkorkmaz & Altintas, 2001) and NURBS interpolators (Cheng & Tsai, 2004;Tsai, Cheng, & Cheng, 2003) the main reported techniques. In addition, FPGA developments of hardware/software architectures for tool path computation have been proposed for spline (De Santiago-Perez, Osornio-Rios, Romero-Troncoso, Cabal-Yepez, & Guevara-Gonzalez, 2010) and NURBS (Cuenca, Martinez, Jimeno, & Sanchez, 2007;Jaen-Cuellar et al, 2012;Yau, Lin, & Tsai, 2006). Yet, these FPGA developments present the implementation of trajectory interpolation for a single interpolation technique.…”

Geração de b-splines via FPGA

“…: : Yau et al (2006) para FPGAs, que resulta na maior eficiência pelo processamento concorrente de circuitos do triângulo do algoritmo Cox-de Boor.…”

“…No método fast Cox-de Boor, proposto por Yau et al (2006) A implementação do método fast Cox-de Boor é executada por meio de circuitos internos que efetuam o processamento do triângulo de Boor, principalmente o cálculo das funções base, conforme mencionado na seção 3.2, dado por α representando o cálculo entre parênteses na equação (21a). As equações 39b e 39c simplificam a equação 10, substituindo a expressão entre parênteses, do segundo termo da equação 10, pela variável α.…”