The thinning engine eliminates the majority of the data and returns only those topological features that are needed for image processing. The image data for thinning must be classified according to the foreground and background. Binary image data becomes the input for thinning. The thinning operation is related to the hit-and-miss transform and can be quite simply expressed in terms of it. Definitions of morphological thinning operations are briefly introduced as follows.Hit and miss are binary morphological operations, the intersection of two sets H a S X and M a S X by the following set translationIn this paper, we present a FPGA-based dedicated parallel thinning architecture proposed in real-time skeletonization system [14]. By synchronizing entire system with single pixel clock, proposed system can generate skeletonized image at frame rate after initial pipeline latency. And we use double buffering for securing time for thinning process. In this case, we can achieve optimum between hardware resource and securing time.This paper is organized as follows. In section 2, we review the previous studies about several approaches to image thinning such as TA, PTA and I-SPTA. The proposed method and its FPGA implementation are presented in section 3 and 4, simultaneously. Experimental results are shown in section 5. In section 6, we conclude the paper and discuss about the future work.Abstract-Thinning is a widely used image processing method which can extract feature parameters from an image. Because of the time complexity caused by repetitive operations of thinning algorithm, many approaches have been done to obtain real-time performance. However, previous thinning algorithms have several limitations for thinning large volumes of data in the processing time aspect. This paper presents parallel thinning architecture and its FPGA-based implementation which can process thinning in real-time. The proposed system is evaluated using large volumes of real-world data and verified its real-time performance.
