Real-time VLSI architecture for detection of moving object using Wronskian determinant

Aguilar-Ponce, Ruth M.; Tessier, Jared; Emmela, C.; Baker, A.; Das, Jadav Chandra; Tecpanecatl-Xihuitl, J. Luis; Kumar, Ashok; Bayoumi, Magdy

doi:10.1109/mwscas.2005.1594241

Cited by 4 publications

(1 citation statement)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Hardware implementations of object recognition algorithms are usually limited by the frame rate or by the area on chip. The FPGA (Field-Programmable Gate Array) based object detection implementation such as in [12] results in a maximum processing speed of 15 frames per second. The complexity and on-chip area is another concern such as presented in retina inspired design [13], and bio-inspired multi-level architecture [14].…”

Section: Introductionmentioning

confidence: 99%

Memristive Threshold Logic Circuit Design of Fast Moving Object Detection

Maan

Kumar²,

Sugathan³

et al. 2015

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Real-time detection of moving objects involves memorisation of features in the template image and their comparison with those in the test image. At high sampling rates, such techniques face the problems of high algorithmic complexity and component delays. We present a new resistive switching based threshold logic cell which encodes the pixels of a template image. The cell comprises a voltage divider circuit that programs the resistances of the memristors arranged in a single node threshold logic network and the output is encoded as a binary value using a CMOS inverter gate. When a test image is applied to the templateprogrammed cell, a mismatch in the respective pixels is seen as a change in the output voltage of the cell. The proposed cell when compared with CMOS equivalent implementation shows improved performance in area, leakage power, power dissipation and delay.

show abstract

Section: Introductionmentioning

confidence: 99%