Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer

doi:10.31838/jvcs/04.02.03

Cited by 10 publications

(10 citation statements)

References 6 publications

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“…Hence, there is drift in transistor manufacture from CMOS to FinFET technology. [27][28][29][30][31][32][33][34][35][36][37][38][39][40]…”

Section: Finfet Characteristics and Modellingmentioning

confidence: 99%

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Data Conversion: Realization of Code converter using Shift Register Modules

2023

VLSI

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Barrel shifter architecture is well known for bit manipulation in a single clock cycle. Due to its various operations and advantages, it is most likely used in the Arithmetic logic unit of every processor. Gray code is also known as reflective code which is widely used in digital communication for the purpose of error correction and error detection. In this project, an 8 x 4 barrel shifter is designed which is further connected to 4-bit binary to gray code converter. The barrel shifter is cascaded with binary to gray code converter so that this combination can be useful for the application of encryption of binary data in digital communications. It is designed in cadence virtuoso tool using FinFET technology at 18 nm node. The simulation results proves that the power consumed by the proposed design with FinFET technology is 11.92% less when compared with the conventional design with MOS transistors. Hence, this design can be used in application of low power digital communications. The functionality testing and verification is done using cadence virtuoso tool.

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“…Hence, there is drift in transistor manufacture from CMOS to FinFET technology. [27][28][29][30][31][32][33][34][35][36][37][38][39][40]…”

Section: Finfet Characteristics and Modellingmentioning

confidence: 99%

“…[11] To improve this architecture, its analysis is carried out using FinFET technology through this paper. [30][31][32][33][34][35][36][37][38][39]…”

mentioning

confidence: 99%

Data Conversion: Realization of Code converter using Shift Register Modules

2023

VLSI

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“…For less than condition, carry out should be equal to 0. [26][27][28][29][30][31][32] The average power, delay and the power-delay product has been calculated. Usually these factors are mostly calculated as they define the optimal circuit performance.…”

Section: Existing Comparatorsmentioning

confidence: 99%

Data Distinguisher Module Implementation using CMOS Techniques

2023

VLSI

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Comparator plays a vital role in many IC applications, Microprocessors, computer systems etc. Hence it is desirable to design a comparator block with low power consumption and high speed performance .In this paper a novel architecture of 32-bit comparator using Complementary metal-oxide semiconductor logic is proposed and computed its delay and power metrics. Further it is compared with the full adder based 32-bit comparator. From the analysis we derive the comparison between proposed and the conventional comparator. The complete designing of architectures and their result analysis was done in cadence virtuoso tool at 180 nm technology. Simulation results show that there is reduce in power consumption of 90% when compared to the conventional full adder based comparator.

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“…The traditional encoder designs present in "flash ADC" consumes more power and has a large delay. [22][23][24][25][26][27][28][29][30][31] Therefore, an advanced model encoder is being proposed in the paper that actually uses/absorbs…”

Section: Introductionmentioning

confidence: 99%

ADC: Novel Methodology for Code Converter Application for Data Processing

2023

VLSI

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An innovative "Multiplexer based Thermometer to Binary code encoder" is presented in this paper. This paper shows a relative decrease in the total count of multiplexers used which eventually reduces the no of transistors used when compared to traditional Architectures. The requirement for further more inverters is also eliminated in the proposed model. The input thermometer code is at first is converted to the respective gray code with the help of 2:1 multiplexer. Thereafter, using two-input XOR gates the conversion process of gray code to respective binary codes takes place. Outcomes of simulation reveal that there is an approximately 80% decrease in the power consumption which is a great reduction actually when differentiated with previously known and current encoder architectures with the delay being reduced from 0.472ps to 0.366 ps. This throws a light on modern power-saving encoder architectures and has a greater significance in the future. The proposed encoder gives a better application for future generation advanced ADC & related circuits.

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Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer

Cited by 10 publications

References 6 publications

Data Conversion: Realization of Code converter using Shift Register Modules

Data Conversion: Realization of Code converter using Shift Register Modules

Data Distinguisher Module Implementation using CMOS Techniques

ADC: Novel Methodology for Code Converter Application for Data Processing

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