Realistic model for the multiple‐input floating‐gate transistor

Abstract

Multiple‐input floating‐gate transistor (FGMOS) circuit designers face a serious problem along the design process: the lack of a realistic simulation model. For this reason, a solution that properly predicts the initial voltage at the floating gates is presented in this paper. In order to assess the performance of the proposal, a comparison is made against a test circuit fabricated in a 0.5‐µm On‐Semiconductor CMOS process. Based on this comparison, the proposed model is shown to be a fundamental tool in the design of FGMOS circuits. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.