Realization of a 1.5 bits/stage pipeline ADC using switched capacitor technique

Ghoshal, Pranati; Sen, Samita

doi:10.1109/icicpi.2016.7859675

Cited by 5 publications

(4 citation statements)

References 12 publications

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“…There are a variety of ADC architectures that implement different approaches to analog-to-digital conversion. Four ADC architectures are evaluated in this work: a pipeline ADC, a cyclic ADC, a ramp ADC, and a Successive Approximation Register (SAR) ADC [18][19][20]. The pipeline and cyclic ADCs chain several low-resolution ADC stages together to produce a higher-resolution ADC.…”

Section: Adc Architecturesmentioning

confidence: 99%

“…It has a much shorter latency than a ramp ADC, but has larger area and is harder to parallelize because the DAC cannot be used for multiple conversions simultaneously. Compared to the pipeline ADC, the SAR ADC has lower throughput but uses less area [18][19][20].…”

Section: Adc Architecturesmentioning

confidence: 99%

“…The pipeline ADC (shown in Fig. 2 (a)) is a multi-stage ADC that uses a succession of 1.5-bit stages to enable high-resolution digitization of the analog input [18]. For example, in an 8-bit ADC, there are seven 1.5-bit stages and a final 1-bit stage.…”

Section: A Pipeline Adcmentioning

confidence: 99%

See 2 more Smart Citations

The Impact of Analog-to-Digital Converter Architecture and Variability on Analog Neural Network Accuracy

Spear,

Kim,

Bennett

et al. 2023

IEEE J. Explor. Solid-State Comput. Devices Circuits

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The analog-to-digital converter (ADC) is a key component in analog in-memory computing accelerators, but also a bottleneck for the efficiency and accuracy of these systems. While the trade-offs between power consumption, latency, and area in ADC design are well studied, it is relatively unknown which ADC implementations are optimal for algorithmic accuracy, particularly for neural network inference. We explore the design space of the ADC with a focus on accuracy, investigating the sensitivity of neural network outputs to component variability inside the ADC and how this sensitivity depends on the ADC architecture. Compact models of the pipeline, cyclic, successiveapproximation-register (SAR) and ramp ADCs are developed, and these models are used in a system-level accuracy simulation of analog neural network inference. Our results show how the accuracy on a complex image recognition benchmark (ResNet50 on ImageNet) depends on the capacitance mismatch, comparator offset, and effective number of bits (ENOB) for each of the four ADC architectures. We find that that robustness to component variations depends strongly on the ADC design, and that inference accuracy is particularly sensitive to the value-dependent error characteristics of the ADC which cannot be captured by the conventional ENOB precision metric.

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Section: Adc Architecturesmentioning

confidence: 99%

Section: Adc Architecturesmentioning

confidence: 99%

See 1 more Smart Citation

The Impact of Analog-to-Digital Converter Architecture and Variability on Analog Neural Network Accuracy

Spear,

Kim,

Bennett

et al. 2023

IEEE J. Explor. Solid-State Comput. Devices Circuits

View full text Add to dashboard Cite

show abstract

“…Switched capacitor circuits work by transporting charge with switches and capacitors instead of resistors, thereby avoiding difficult-to-integrate resistors in integrated circuits [2][3][4]. The SC circuit has many good characteristics such as high precision time constant, good voltage linearity, good temperature characteristic, compatible CMOS process, so it has been widely implemented in many vital parts of analog circuit such as pipeline Analog to Digital Converter (ADC), DC-DC converter, Switched capacitor filter [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

A design of fully differential operational amplifier for switched-capacitor application

Niu

2023

HSET

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Switched-capacitor (SC) circuit is used widely in communication and signal processing systems, such as switched-capacitor filter and switched-capacitor integrator. This paper proposes a fully differential operational amplifier for switched-capacitor application. The designed amplifier comprises common mode feedback circuit, auxiliary amplifier and main amplifier using fold cascode structure and its biasing circuit. The supply voltage VDD is 1V and VSS is -1V. After the simulation using TSMC 0.18μm process model, the simulation result shows the proposed amplifier achieve about 100.6dB DC gain, 66 degree phase margin,333 MHz unit gain bandwidth, 3.78V differential output swing, 287V/μs slew rate,122.8 dB DC PSRR, 114 dB DC CMRR, 1.6mW power consumption, the input reference noise is about 6nV/√Hz at 1MHz, the Total Harmonic Distortion of this amplifier is less than about 1.05%.The proposed fully differential operation amplifier meet all the specification, and it can be used in some SC circuit applications.

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A new ripple carry adder structure based on a swing‐boosted full adder for concurrent error correction in low‐resolution pipeline analog‐to‐digital converters

Tahghigh,

Shiri

2024

Circuit Theory & Apps

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SummaryA ripple carry adder (RCA) structure is presented which can concurrently correct a gain error in low‐resolution pipeline analog‐to‐digital converters (ADCs). The RCA is composed of a new swing‐boosted full adder (FA) based on the transmission gate (TG) technique. So, it is low‐power, high‐speed, and full‐swing with high driving capability. In 90 nm technology, the results of power, delay, and power‐delay‐product (PDP) of the FA are 1.5296 μW, 2.1141 ns, and 3.2337 fJ, respectively. The RCA with an area of 408.09 μm2 is evaluated by a 3‐bit pipeline ADC with 1.5‐bit per stage. When the erroneous codes are passed through the RCA, the maximum and minimum integral nonlinearity (INL) are improved by 19.83% and 90.98%, while the maximum and minimum of the differential nonlinearity (DNL) are improved by 50%, and 42.06%, respectively.

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Realization of a 1.5 bits/stage pipeline ADC using switched capacitor technique

Cited by 5 publications

References 12 publications

The Impact of Analog-to-Digital Converter Architecture and Variability on Analog Neural Network Accuracy

The Impact of Analog-to-Digital Converter Architecture and Variability on Analog Neural Network Accuracy

A design of fully differential operational amplifier for switched-capacitor application

A new ripple carry adder structure based on a swing‐boosted full adder for concurrent error correction in low‐resolution pipeline analog‐to‐digital converters

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