Realization of a programmable parallel DSP for high performance image processing applications

Wittenburg, Jens; Berekovic, Mladen; Hinrichs, W.; Lieske, Hanno; Kneip, J.; Kloos, H.; Ohmacht, Martin; Pirsch, P.

doi:10.1145/277044.277055

Cited by 9 publications

(4 citation statements)

References 4 publications

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“…Instruction-set extensions can be used to efficiently speedup a variety of algorithms, such as variable-length (entropy) decoding, cryptography or bitstream processing. Most of today_s processors and DSPs implement SIMD-style instruction-set extensions [36][37][38][39].…”

Section: Architecture Requirements For Embedded Dsp Processingmentioning

confidence: 99%

A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance

Berekovic

Niggemeier

2007

J Sign Process Syst Sign Image

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A scalable, distributed, processor architecture is presented that emphasizes on high performance computing for digital signal processing applications by combining high frequency design techniques with a very high degree of parallel processing on a chip. The architecture is based on a superscalar processor model with a modified Tomasulo scheme that was extended to eliminate all central control structures for the data flow and to support simultaneous instruction issue from multiple independent threads [simultaneously multi-threaded (SMT)]. Consequent application of fine clustering reduces the cycle-time for wire-sensitive building blocks of the processor like the register file and the scheduling window and leads to a distributed architecture model, where independent thread processing units, arithmetic logic units, registers files and memories are distributed across the chip and communicate with each other by special network. A special communication protocol replaces broadcasting and associative compare of destination tags in a centralised instruction scheduler with explicit operand transfer instructions, thus decentralizing the control of the data flow to the greatest extent. As a result, the processor cycle time does neither depend on the issue bandwidth of a single thread nor on the execution bandwidth of the SMT processor. This makes the performance of the architecture scalable with both the number of function and the number of thread units without having any impact on the processors cycle-time. Performance and scalability of the proposed microarchitecture is demonstrated with critical signal processing kernels from the MPEG-4 video coding standard on a cycle-true simulator.

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Section: Architecture Requirements For Embedded Dsp Processingmentioning

confidence: 99%

A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance

Berekovic

Niggemeier

2007

J Sign Process Syst Sign Image

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“…In addition to VDs, parallel architectures have been applied to numerous computation-intensive DSP problems [11], [16], [28], [35]. In such systems, multiple computation and memory units operate in parallel to achieve high throughput and low power [22].…”

Section: B Low-power Parallel Dsp System Designmentioning

confidence: 99%

Design of a 20-mb/s 256-state Viterbi decoder

Liu

Papaefthymiou

2003

IEEE Trans. VLSI Syst.

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The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often consist of long interconnect wires, resulting in large area and high power consumption. In this paper, we propose a data transfer oriented design methodology to implement a low-power 256-state rate-1/3 Viterbi decoder. Our architectural level scheme uses operation partitioning, packing, and scheduling to analyze and optimize interconnect effects in early design stages. In comparison with other published Viterbi decoders, our approach reduces the global data transfers by up to 75% and decreases the amount of global buses by up to 48%, while enabling the use of deeply pipelined datapaths with no data forwarding. In the register-transfer level (RTL) implementation, we apply precomputation in conjunction with saturation arithmetic to further reduce power dissipation with provably no coding performance degradation. Designed using a 0.25 m standard cell library, our decoder achieves a throughput of 20 Mb/s in simulation and dissipates only 0.45 W.

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“…In addition to VDs, parallel architectures have been applied to numerous computation-intensive DSP problems [7,10,19,24]. In such systems, multiple computation and memory units operate in parallel to achieve high throughput and low power [13].…”

Section: Low-power Parallel Dsp System Designmentioning

confidence: 99%

Design of a high-throughput low-power IS95 Viterbi decoder

Liu

Papaefthymiou

2002

Proceedings of the 39th Conference on Design Automation - DAC '02

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The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often consist of long interconnect wires, resulting in large area and high power consumption. In this paper, we propose a data-transfer oriented design methodology to implement a low-power 256-state rate-1/3 IS95 Viterbi decoder. Our architectural level scheme uses operation partitioning, packing, and scheduling to analyze and optimize interconnect effects in early design stages. In comparison with other published Viterbi decoders, our approach reduces the global data transfers by up to 75% and decreases the amount of global buses by up to 48%, while enabling the use of deeply pipelined datapaths with no data forwarding. In the RTL implementation of the individual processors, we apply precomputation in conjunction with saturation arithmetic to further reduce power dissipation with provably no coding performance degradation. Designed using a 0.25 µm standard cell library, our decoder achieves a throughput of 20 Mbps in simulation and dissipates only 450 mW.

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Realization of a programmable parallel DSP for high performance image processing applications

Cited by 9 publications

References 4 publications

A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance

A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance

Design of a 20-mb/s 256-state Viterbi decoder

Design of a high-throughput low-power IS95 Viterbi decoder

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