Realization of block floating-point digital filters and application to block implementations

Ralev, K.; Bauer, Péter

doi:10.1109/78.752605

Cited by 29 publications

(13 citation statements)

References 25 publications

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“…Unfortunately, standard fixed-point processors typically suffer from relatively low dynamic range (DR), and great care must therefore be taken in dealing with finite word-length effects such as quantization noise, overflow, and limit cycles [9]- [11]. Several alternative number formats and associated hardware implementations have therefore been proposed; these include floating point, block floating point (BFP) [12]- [14], and the logarithmic number system (LNS) [15]- [17].…”

Section: Overview Of Number Formats and Companding For Dspsmentioning

confidence: 99%

Externally Linear Discrete-Time Systems With Application to Instantaneously Companding Digital Signal Processors

Klein

Tsividis

2011

IEEE Trans. Circuits Syst. I

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We present a technique for applying arbitrary invertible nonlinear functions to the internal signals of a prototype linear time-invariant digital signal processor, without causing any output disturbances. By using our proposed technique, the external input-output behavior of the DSP remains linear, and identical to that of the prototype, despite the nonlinear behavior of its internal signals. We explore the specific application of our technique to instantaneous companding, in which the introduced nonlinearities compress the dynamic range of the internal signals, so that the latter span most of the available bits in the system, thus improving the signal-to-noise-plus-distortion-ratio at the output, for low to medium input signal levels. We discuss the choice of nonlinear functions for this companding application, and we present an efficient hardware implementation for the standard 15-segment piecewise-linear approximation to the 255-law. We compare the performance and hardware overhead of our technique with that of other companding architectures.Index Terms-Companding systems, externally linear systems, internally nonlinear systems, fixed-point arithmetic, quantization.

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Section: Overview Of Number Formats and Companding For Dspsmentioning

confidence: 99%

Externally Linear Discrete-Time Systems With Application to Instantaneously Companding Digital Signal Processors

Klein

Tsividis

2011

IEEE Trans. Circuits Syst. I

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“…In other words, not all 30 b are necessary for arithmetic. These two observations suggest a floating-point data format, which is composed of mantissa for precision and exponent for magnitude, as the best candidate for signal processing in the adaptation blocks [16]- [18].…”

Section: B Floating-point Signal Processingmentioning

confidence: 97%

A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios

Yang

Čabrić

et al. 2012

IEEE J. Solid-State Circuits

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A digital baseband cognitive radio spectrum sensing processor with 200-kHz resolution over 200-MHz bandwidth is integrated in 1.64 mm in 65-nm CMOS. The processor uses adaptive channel-specific threshold and sensing time to achieve detection probability 0.9 and false-alarm probability 0.1 for 5-dB SNR and adjacent-band interferers of 30-dB INR within a 50-ms sensing time. The chip power and area are minimized by jointly considering algorithm, architecture, and circuit parameters. The chip dissipates 7.4 mW for a 200-MHz sensing bandwidth, which is a 22 reduction in power per sensing bandwidth compared with prior work.Index Terms-CMOS digital integrated circuits, cognitive radio (CR), power and area minimization, wideband spectrum sensing.

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“…Overflow or underflow occurs when the bits for the exponent part are not sufficient. The effects of finite-precision floating-point implementation have been well studied in digital filter designs (Kallioja¨rvi and Astola 1996, Rao 1996, Ralev and Bauer 1999. However, there has been relatively little work studying explicitly floating-point digital controller implementations.…”

Section: Introductionmentioning

confidence: 99%

Optimal realizations of floating-point implemented digital controllers with finite word length considerations

Chen

Whidborne

et al. 2004

International Journal of Control

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The closed-loop stability issue of finite word length (FWL) realizations is investigated for digital controllers implemented in floating-point arithmetic. Unlike the existing methods which only address the effect of the mantissa bits in floatingpoint implementation to the sensitivity of closed-loop stability, the sensitivity of closed-loop stability is analysed with respect to both the mantissa and exponent bits of floating-point implementation. A computationally tractable FWL closed-loop stability measure is then defined, and the method of computing the value of this measure is given. The optimal controller realization problem is posed as searching for a floating-point realization that maximizes the proposed FWL closed-loop stability measure, and a numerical optimization technique is adopted to solve for the resulting optimization problem. Simulation results show that the proposed design procedure yields computationally efficient controller realizations with enhanced FWL closed-loop stability performance.

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Realization of block floating-point digital filters and application to block implementations

Cited by 29 publications

References 25 publications

Externally Linear Discrete-Time Systems With Application to Instantaneously Companding Digital Signal Processors

Externally Linear Discrete-Time Systems With Application to Instantaneously Companding Digital Signal Processors

A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios

Optimal realizations of floating-point implemented digital controllers with finite word length considerations

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