2016
DOI: 10.5815/ijcnis.2016.07.08
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Realization of Efficient High Throughput Buffering Policies for Network on Chip Router

Abstract: Abstract-The communication between processing elements is suffering challenges due to power, area and latency. Temporary flit storage during communication consumes the maximum power of the whole power consumption of the chip. The majority of current NoCs consume a high amount of power and area for router buffers only. Removing buffers and virtual channels (VCs) significantly simplifies router design and reduces the power dissipation by a considerable amount. The buffering scheme used in virtual channeling in a… Show more

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Cited by 2 publications
(2 citation statements)
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“…In Ex (Execute Stage) the functional units process the task and store its result back into a record file. Finally, the commit stage retires instructions from the ROB in program order [20][21][22][23][24]. This processing flowchart is comparative to the one designed by the SimpleScalar tool set [8].…”
Section: Multi-processing and Pipelining During Simulationmentioning
confidence: 99%
“…In Ex (Execute Stage) the functional units process the task and store its result back into a record file. Finally, the commit stage retires instructions from the ROB in program order [20][21][22][23][24]. This processing flowchart is comparative to the one designed by the SimpleScalar tool set [8].…”
Section: Multi-processing and Pipelining During Simulationmentioning
confidence: 99%
“…There is no mature comparison between various elastic designs and elastic handshaking protocols in terms of performance. Moreover, none of the studies does explore performance with new technology challenges under process variation [18].…”
Section: Introductionmentioning
confidence: 99%