Realization of OFDM Modulator and Demodulator for DSRC Vehicular Communication System Using FPGA Chip

Abstract

Following the DSRC vehicular communications code is completed before the next line is executed, extending IEEE802.11p physical layer standards, this paper presents the the time required to complete an operation when the load is required computing time estimations of baseband processing large. On the other hand, the FPGA chip utilizes tens of modules on the DSP platform and uses this estimation to explain thousands of lists and triggers during operation. After the decision of choosing to implement the 64 point IFFT/FFT module with the FPGA chip. The IFFT/FFT processing time of programming in Verilog-HDL [4], circuit-like structures can OFDM modulator/demodulator circuits in applications of DSRC be data ssmcalculytione, so perous logic gates can vehicular communication system transceivers must be less than process data simultaneously in one clock pulse, resulting in a the symbol interval of 8,usec in order to satisfy the requirement of parallel processing system, putting the FPGA computing real-time DSRC communications. The 64-IFFT/FFT processing speed at a significant advantage over the DSP chip's speed. module presented in this paper uses a parallel processing Another advantage of FPGA chips is its lower power structure of four butterfly circuit units, is capable of processing consumption compared with DSP chips. 16-bit digital signals, and completes 64-IFFT/FFT calculations inWhen transceiver baseband processing is implemented with 5.33,usec (< 8,usec) with a 24 MHz FPGA chip. Ten short DSPs, most of the clock cycles are used in computing the training symbols of the DSRC system are sent through the FPGA inverse fast Fourier transform (IFFT) and fast Fourier IFFT/FFT module to verify its functionality and performance.transform (FFT) operations as shown in Table I, where the DSP clock rate is 167 MHz, and 20 data symbols are received I. INTRODUCTION (using 16-QAM modulation); the FFT module and the The "Dedicated Short Range Communication (DSRC) frequency domain equalizer (FEQ) take up 53.16% and System" [1][2][3] is a type of high-speed mobile broadband 29.95% of the total time of computation [5]. For this reason, wireless communication system developed for electronic we will use FPGA chips to implement the FFT and FEQ highway toll collection. This system integrates technologies modules, in order to satisfy the requirements for DSRC in communications, networking, and sensors, and is capable of transceiver baseband processing. not only monitoring highway traffic conditions and electronic This paper follows the IEEE802.1tp physical layer toll collection, sending vehicle information to traffic control standards for DSRC vehicular communication systems [1], centers in order to provide various information services, but using the FPGA chip to create the 64-IFFT/FFT processing can also be used to provide services such as vehicle module to implement the orthogonal frequency division positioning and payment for gasoline stations or parking lots multiplexing (OFDM) modulation/demodulation circuit in in everyday circumstanc...