Realizing a robust, reconfigurable active quenching design for multiple architectures of single-photon avalanche detectors

Abstract

Most active quench circuits used for single-photon avalanche detectors are designed either with discrete components which lack the flexibility of dynamically changing the control parameters, or with custom ASICs which require a long development time and high cost. As an alternative, we present a reconfigurable and robust hybrid design implemented using a System-on-Chip (SoC), which integrates both an FPGA and a microcontroller. We take advantage of the FPGA's speed and configuration capabilities to vary the quench and reset parameters dynamically over a large range, thus allowing our circuit to operate with a wide variety of APDs without having to re-design the system. The microcontroller enables the remote adjustment of control parameters and re-calibration of APDs in the field. The ruggedized design uses components with space heritage, thus making it suitable for space-based applications in the fields of telecommunications and quantum key distribution (QKD). We characterize our circuit with a commercial APD cooled to -20°C, and obtain a deadtime of 35ns while maintaining the after-pulsing probability at close to 3%. We also demonstrate versatility of the circuit by directly testing custom fabricated chip-scale APDs, which paves the way for automated wafer-scale testing and characterization.

Modeling for Single-Photon Avalanche Diodes: State-of-the-Art and Research Challenges

“…Recently, active quenching and reset (AQR) configurations have been widely used due to their fast response, small area, and configurable dead time. The quenching and resetting times have evolved from the microseconds range in passive configuration to several nanoseconds in recent active configurations [ 28 , 102 , 103 , 104 , 105 , 106 , 107 , 108 , 109 , 110 ]. To simulate the performance of these advanced front-end circuits, SPAD circuit models are needed.…”

Performance of Active-Quenching SPAD Array Based on the Tri-State Gates of FPGA and Packaged with Bare Chip Stacking

“…Samuel Burri et al reported a compact linear SPAD camera system with commercial FPGA-based TDC modules for versatile 50 ps resolution timeresolved imaging; however, the variable-load quenching circuit used to implement the quenching process of the SPAD array was designed based on ASIC technology [9]. Subash Sachidananda et al reported a reconfigurable hybrid design implemented by a System-on-Chip (SoC), which integrates an FPGA to vary the quench and reset parameters; however, it practically belongs to the ASIC-based AQC category [10].…”