2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC) 2014
DOI: 10.1109/vlsi-soc.2014.7004183
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Realizing a security aware triple modular redundancy scheme for robust integrated circuits

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Cited by 10 publications
(4 citation statements)
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“…The use of TMR to thwart HT insertion has been proposed in [10], [4], [5] by N. Gunti et al In such a TMR based method, an HT has to be introduced in at least two copies in order not to be blocked by the majority voter. Authors claim that such duplication of a potential HT makes it relatively big, therefore also relatively easy to detect through side-channel based techniques.…”
Section: B Ht Prevention Methods Based On Redundancymentioning
confidence: 99%
See 1 more Smart Citation
“…The use of TMR to thwart HT insertion has been proposed in [10], [4], [5] by N. Gunti et al In such a TMR based method, an HT has to be introduced in at least two copies in order not to be blocked by the majority voter. Authors claim that such duplication of a potential HT makes it relatively big, therefore also relatively easy to detect through side-channel based techniques.…”
Section: B Ht Prevention Methods Based On Redundancymentioning
confidence: 99%
“…As in other similar works that use TMR as neutralization method [10], [4], [5], we have selected the ISCAS'85 benchmarks as target circuits [12]. We have selected two circuits -c499 and c7552 -based on their different sizes and functionalities, to carry out a thoroughly study about the proposed approach.…”
Section: A Methodologymentioning
confidence: 99%
“…In the past decade, there are many hardware Trojan detection works, including the side-channel analysis based detection approaches [5]- [9] and logic testing approaches [10], [11]. Some design-for-security approaches are also proposed to facilitate hardware Trojan detection or prevent hardware Trojan insertion, e.g., built-in self-authentication technique to prevent inserting hardware Trojans [12], redundancy-based protection approach based on Trojan tolerance that modifies the application mapping process to provide high-level of protection against Trojans in FPGA [13], the approach promoting smart employment of circuit redundancy to counter Trojans in 3PIP cores [14], and the approach using a selective Triple Modular Redundancy (TMR) scheme to mask the effect of Trojans along with transient errors [15]. Most of them require golden chips or golden models for reference.…”
Section: Introductionmentioning
confidence: 99%
“…for j = 1 to R do 15: initialize the disagreement measure matrix DIS l×(R−l) and average disagreement measure vector aver 1×(R−l) to be 0 in aver (denoted as aver j ). Then the basic algorithm which has the maximum value in aver is removed from ∂ and added to∂.…”
mentioning
confidence: 99%