REC-STA: Reconfigurable and Efficient Chip Design With SMO-Based Training Accelerator

Peng, Chih-Hsiang; Chen, Bo-Wei; Kuan, Ta-Wen; Lin, Po-Chuan; Wang, Jhing-Fa; Shih, Nai-Sheng

doi:10.1109/tvlsi.2013.2278706

Cited by 11 publications

(19 citation statements)

References 31 publications

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“…This method provides guidance for online training of SVM. For the key steps of SMO to satisfy Karush-Kuhn-Tucher (KKT) conditions during training, Jhing-Fa Wang et al studied the implementation of SMO, which includes Intellectual Property (IP) core implementation of SMO [16], an efficient configurable chip design based on SMO acceleration training method [17], and implementation of a low cost trainable SMO mode classifier [18]. The above research adopts a development method close to the underlying layer.…”

Section: Introductionmentioning

confidence: 99%

Research and Implementation of ε-SVR Training Method Based on FPGA

Liu

et al. 2019

Electronics

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Online training of Support Vector Regression (SVR) in the field of machine learning is a computationally complex algorithm. Due to the need for multiple iterative processing in training, SVR training is usually implemented on computer, and the existing training methods cannot be directly implemented on Field-Programmable Gate Array (FPGA), which restricts the application range. This paper reconstructs the training framework and implementation without precision loss to reduce the total latency required for matrix update, reducing time consumption by 90%. A general ε-SVR training system with low latency is implemented on Zynq platform. Taking the regression of samples in two-dimensional as an example, the maximum acceleration ratio is 27.014× compared with microcontroller platform and the energy consumption is 12.449% of microcontroller. From the experiments for the University of California, Riverside (UCR) time series data set. The regression results obtain excellent regression effects. The minimum coefficient of determination is 0.996, and running time is less than 30 ms, which can meet the requirements of different applications for real-time regression.

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Section: Introductionmentioning

confidence: 99%

Research and Implementation of ε-SVR Training Method Based on FPGA

Liu

et al. 2019

Electronics

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“…However, the specific hardware implementations, including SMO learning [10][11][12][13], LPCC extraction [14,15] and SVM classification [16][17][18][19][20], are at the component level and do not support system-level simulation or verification. This investigation improves components [10][11][12][13][14][15][16][17][18][19][20] by developing a novel and comprehensive SoC design that can be used in real time but does not have a substantially larger area. Relevant corresponding VLSI studies [10][11][12][13][14][15][16][17][18][19][20] are discussed below.…”

Section: Introductionmentioning

confidence: 99%

“…This investigation improves components [10][11][12][13][14][15][16][17][18][19][20] by developing a novel and comprehensive SoC design that can be used in real time but does not have a substantially larger area. Relevant corresponding VLSI studies [10][11][12][13][14][15][16][17][18][19][20] are discussed below.…”

Section: Introductionmentioning

confidence: 99%

“…Recent hardware realisations of SMO VLSI designs are reported in [10][11][12][13]. Keerthi et al [10] developed the parallel processing of partitioned data sets on 32 power PC_POWER4 1.3 GHz CPUs.…”

Section: Introductionmentioning

confidence: 99%

“…Kuan et al [12] presented a new hardware architecture for an SMO learning accelerator, but it did not have real-time learning capability. The proposed SoC also integrates the reconfigurable architecture used in our previous work [13] to enable real-time learning capability without excessively increasing chip area.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Low‐power enhanced system‐on‐chip design for sequential minimal optimisation learning core with tri‐layer bus and butterfly‐path accelerator

Peng

Lin

Barma

et al. 2015

IET Computers & Digital Techniques

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A tri-layer bus system-on-chip (SoC) and a butterfly-path accelerator are used to enhance system-level performance in a sequential minimal optimisation learning core. The tri-layer bus architecture is used to obtain an adequate transfer rate. The butterfly-path accelerator also uses symmetrical access to resolve bottlenecks during linear prediction cepstral coefficients extraction. This novel design increases speed and flexibility without substantially increasing area. For implementation in chip manufacturing, the SoC is synthesised, placed and routed using the TSMC 90 nm technology library. The die size is 2.09 mm × 2.09 mm, and the power consumption is 8.9 mW. Compared with the non-butterfly-path design, the simulation results show that the proposed architecture provides a 2.4-fold speed increase. In addition, clock down-sampling and voltage scaling reduce the power consumed by the proposed chip by a factor of 8.5. The experimental results confirm the improved speed and power that are provided by the proposed architecture and methods.

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