2011
DOI: 10.1155/2011/982314
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Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links

Abstract: High-speed links which employ source synchronous clocking architectures have the ability to track correlated jitter between clock and data channels up to high frequencies. However, system timing margins are degraded by channel skew between clock and data signals and high-frequency loss. This paper describes how these key channel effects impact the jitter performance and influence the clocking architecture of high-speed source synchronous links. Tradeoffs in complexity and jitter tracking performance of common … Show more

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Cited by 18 publications
(6 citation statements)
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References 27 publications
(36 reference statements)
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“…A reasonable choice of the design parameters was made in this work, and the JTOL curve resulting from ( 4) is comparable with published work [21]. The use of phase-detection from one channel in the updating of the PR code in another channel raises the question of whether the correlation of data jitter seen on adjacent channels leads to detrimental differential jitter, because of the difference in data path length and REF_CK path length between channels [22]. A delay mismatch due to combined data path and REF_CK path length differences between channels could exceed a few UIs over a 100 m interconnect.…”
Section: Cdr Loop Dynamics Stability and Inter-lane Trackingsupporting
confidence: 63%
“…A reasonable choice of the design parameters was made in this work, and the JTOL curve resulting from ( 4) is comparable with published work [21]. The use of phase-detection from one channel in the updating of the PR code in another channel raises the question of whether the correlation of data jitter seen on adjacent channels leads to detrimental differential jitter, because of the difference in data path length and REF_CK path length between channels [22]. A delay mismatch due to combined data path and REF_CK path length differences between channels could exceed a few UIs over a 100 m interconnect.…”
Section: Cdr Loop Dynamics Stability and Inter-lane Trackingsupporting
confidence: 63%
“…As an alternative, we would rather start modifying the golden architecture. One of the potential candidates is a forwarded-clock architecture, which has been explored in several literatures ( Casper et al, 2006 ; Li et al, 2014 ; Ragab et al, 2011 ; Casper & O’Mahony, 2009 ; Hossain & Carusone, 2011 ; Chung & Kim, 2012 ; Bae et al, 2016 ). The bit-error-rate (BER) of an interconnect is a function of the amplitude noise (SNR) and the timing noise (jitter) ( Bae et al, 2016 ).…”
Section: Interconnectmentioning
confidence: 99%
“…2(c), the clock-jitter filter increases a dynamic timing margin by giving up to track highfrequency data jitter. For the clock-jitter filter, the optimal jitter-tracking bandwidth (JTB) for the dynamic timing margin is determined by the latency mismatch ( T ) [10] f JTB|opt = 1/(6 T ).…”
Section: Architecture Reviewmentioning
confidence: 99%