Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs

Jiang, Dongyang; Sin, Sai-Weng; Qi, Liang; Wang, Guoxing; Martins, Rui P.

doi:10.1109/ojsscs.2021.3118668

Cited by 8 publications

(2 citation statements)

References 39 publications

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“…The noise-shaping(NS) SAR ADC is a hybrid architecture of SAR ADC and ΔΣ ADC. It integrates the oversampling and noise shaping techniques to suppress quantization/comparator noise and relax the CDAC size, thus enabling high resolution while maintaining low power consumption [11,12,13]. The design of loop filters is directly related to the effect of NS, which is also the key to the circuit design of NS-SAR ADCs.…”

Section: Introductionmentioning

confidence: 99%

A second-order CIFF noise-shaping SAR ADC reusing a dynamic amplifier

Wang,

Chen,

Zhou

et al. 2024

IEICE Electron. Express

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This article presents a second-order cascaded integrator feedforward (CIFF) noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) reusing a dynamic amplifier. The proposed NS architecture uses a gain-optional floating inverter amplifier (FIA) and sampling-before-integrating technique, realizing a sharp noise transfer function (NTF) with extra capacitance of 1.4 times capacitive digital-to-analog converter(CDAC). Implemented in 180-nm CMOS technology, the proposed NS-SAR ADC achieves a signal-to-noisedistortion ratio (SNDR) of 88.6 dB over a sampling frequency of 1.6 MHz and an oversampling rate (OSR) of 16 while consuming only 250 𝜇W. It results in an SNDR-based Schreier figure-of-merit (FoM) of 171.6 dB, proving the proposed ADC fulfils considerable performance with both high resolution and low power consumption.

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Section: Introductionmentioning

confidence: 99%

A second-order CIFF noise-shaping SAR ADC reusing a dynamic amplifier

Wang,

Chen,

Zhou

et al. 2024

IEICE Electron. Express

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show abstract

“…High-resolution analog-to-digital (A/D) converters (ADCs) are relevant building blocks in different IoT systems. Applications such as high-precision sensor networks, communications, imaging, and signal processing require outstanding ADC performance, including high-accuracy, low-power consumption, and, in some cases, wide-bandwidth (BW) specifications [2].…”

Section: Introductionmentioning

confidence: 99%

All-Standard-Cell-Based Analog-to-Digital Architectures Well-Suited for Internet of Things Applications

Correia

Tavares

Barquinha

et al. 2022

JLPEA

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In this paper, the most suited analog-to-digital (A/D) converters (ADCs) for Internet of Things (IoT) applications are compared in terms of complexity, dynamic performance, and energy efficiency. Among them, an innovative hybrid topology, a digital–delta (Δ) modulator (ΔM) ADC employing noise shaping (NS), is proposed. To implement the active building blocks, several standard-cell-based synthesizable comparators and amplifiers are examined and compared in terms of their key performance parameters. The simulation results of a fully synthesizable Digital-ΔM with NS using passive and standard-cell-based circuitry show a peak of 72.5 dB in the signal-to-noise and distortion ratio (SNDR) for a 113 kHz input signal and 1 MHz bandwidth (BW). The estimated FoMWalden is close to 16.2 fJ/conv.-step.

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A 62.5 kHz-BW 92 dB-SNDR noise-shaping SAR ADC with NS-CAL method

Li,

Zhao,

et al. 2024

Microelectronics Journal

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Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs

Cited by 8 publications

References 39 publications

A second-order CIFF noise-shaping SAR ADC reusing a dynamic amplifier

A second-order CIFF noise-shaping SAR ADC reusing a dynamic amplifier

All-Standard-Cell-Based Analog-to-Digital Architectures Well-Suited for Internet of Things Applications

A 62.5 kHz-BW 92 dB-SNDR noise-shaping SAR ADC with NS-CAL method

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