Recent research development and new challenges in analog layout synthesis

Chang, Yao‐Wen; Hung, Chih‐Ming

doi:10.1109/aspdac.2016.7428080

Cited by 39 publications

(12 citation statements)

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“…Analog building block identification is an important task in design automation for analog ICs. It helps understand analog circuit structures and functionalities for topology synthesis [5], facilitate circuit simulation and sizing [8,16], and accelerate analog layout synthesis [13]. For example, in analog layout synthesis, some devices of an analog circuit may form a matching group, a symmetry group, or a proximity group.…”

Section: Building Block Classification and Identificationmentioning

confidence: 99%

Achieving analog layout integrity through learning and migration

Chi

Patyal

Liu

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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Section: Building Block Classification and Identificationmentioning

confidence: 99%

Achieving analog layout integrity through learning and migration

Chi

Patyal

Liu

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

Self Cite

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“…To achieve this task, the capability to deal with layout constraints, in order to decrease unwanted parasitics due to the fabrication process, is mandatory. [1] enumerates the most common placement constraints that are respected by modern analog placer where symmetries [2] are the most used constraints.…”

Section: Background Of the Problemmentioning

confidence: 99%

Semi-automated analog placement

Lao

Louërat

Chaput

2016

2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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“…However, they still deal with the effects of interconnect (i.e., route) parasitic elements as second order effects ignoring that the interconnect parasitic effects became one of the dominant factors on a circuit performance in advanced process nodes, especially those parasitic effects that are associated with critical nets. In order to control the effects of parasitic elements, the corresponding routes need to be routed in a way that reduces the associated parasitic elements [5], [6].…”

Section: Introductionmentioning

confidence: 99%

RC Parasitic-Aware Layout Analysis and Routing Optimization Methodology

Abouelyazid

Hammouda²,

Ismail

2022

IEEE Access

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A parasitic-aware routing optimization and analysis methodology for integrated circuits is developed based on an incremental parasitic extraction and a fast optimization methodology. Existing routing optimization methodologies rely on many circuit simulations, detailed sensitivity analysis, and inefficient simple parasitic models to optimize routes. Moreover, they do not provide a mechanism to help layout designers in identifying problematic layout geometries that have a bad impact on a route's performance. The proposed methodology works on overcoming such problems by providing three features. First, it provides novel sensitivity circuit models to analyze the integrity of signals in layout routes. Such circuit models are based on an accurate matrix circuit representation, a cost function, and an accurate parasitic sensitivity extraction. The circuit models identify critical parasitic elements along with the corresponding layout geometries in a certain route, where they measure the sensitivity of a route's performance to corresponding layout geometries very fast. Therefore, they can correlate the problems of a route's performance to specific layout geometries. Second, the proposed methodology uses a nonlinear programming technique to optimize problematic routes with pre-determined degrees of freedom using the proposed circuit models. Third, the proposed methodology uses a novel incremental parasitic extraction method to extract parasitic elements of modified geometries efficiently. The incremental extraction is used as a part of the routing optimization process to improve the optimization runtime and increase the optimization accuracy. The proposed methodology is tested over different designs of 7nm and 65nm process nodes. The results show that the proposed methodology managed to identify and optimize the problematic geometries in critical routes efficiently with up to 10% performance improvements and a speedup of 3 to 9X as compared to traditional template-based methods.

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Recent research development and new challenges in analog layout synthesis

Cited by 39 publications

References 50 publications

Achieving analog layout integrity through learning and migration

Achieving analog layout integrity through learning and migration

Semi-automated analog placement

RC Parasitic-Aware Layout Analysis and Routing Optimization Methodology

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