2022
DOI: 10.3390/electronics11182914
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Recent Trends in Copper Metallization

Abstract: The Cu/low-k damascene process was introduced to alleviate the increase in the RC delay of Al/SiO2 interconnects, but now that the technology generation has reached 1× nm or lower, a number of limitations have become apparent. Due to the integration limit of low-k materials, the increase in the RC delay due to scaling can only be suppressed through metallization. As a result, various metallization methods have been proposed, including traditional barrier/liner thickness scaling, and new materials and integrati… Show more

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Cited by 22 publications
(10 citation statements)
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“…For the double‐Damascene structure (a trench overlying a via), both the trench and via need to be filled with the Ta film at the same time in industry. However, due to the practical difficulties to prepare such complex double‐Damascene structure, [ 20 ] we instead evaluated the uniformity and conformality of the PEALD Ta films separately in trenches and vias.…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…For the double‐Damascene structure (a trench overlying a via), both the trench and via need to be filled with the Ta film at the same time in industry. However, due to the practical difficulties to prepare such complex double‐Damascene structure, [ 20 ] we instead evaluated the uniformity and conformality of the PEALD Ta films separately in trenches and vias.…”
Section: Resultsmentioning
confidence: 99%
“…For the double-Damascene structure (a trench overlying a via), both the trench and via need to be filled with the Ta film at the same time in industry. However, due to the practical difficulties to prepare such complex double-Damascene structure, [20] we instead evaluated the uniformity and conformality of the PEALD Ta films separately in trenches and vias. Figure 5a,f shows the schematics and top-view SEM images of the trench and via areas, and Figure 5b,g shows the crosssectional annular bright field (ABF) scanning transmission electron microscopy (STEM) images for a trend and a via covered by the PEALD Ta films.…”
Section: Application Of Ta Films For Cu Interconnectsmentioning
confidence: 99%
“…To be compatible with the process temperature limit of BEOL (⩽400 • C), the thinfilm coatings can be prepared by PALD. In the damascene Cu process, TaN, Ta, and Cu metals are used as the barrier, liner, and seed layers, respectively [307]. All these metals can be prepared by PALD.…”
Section: Metal Interconnectsmentioning
confidence: 99%
“…Cu 2+ + 2e − Cu 0 (16) Electrons are produced due to the reaction of formaldehyde with OHions on the copper surface, which in turn reduce Cu 2+ ions into Cu 0 .…”
Section: Zno Thin-film-based Electroless Depositionmentioning
confidence: 99%
“…Both thin and thick metal layers are deposited to create planer interconnect lines, known as redistribution lines (RDL). Owing to its superior electrical and thermal conductivity and higher electromigration resistance, copper is extensively used as interconnect material in these applications [12][13][14][15][16]. While the critical dimensions in microelectronics are scaled below 7 nm, deposition of high-quality copper thin films is often required.…”
Section: Introductionmentioning
confidence: 99%