Reconfigurable architecture for computing histograms in real-time tailored to FPGA-based smart camera

Maggiani, Luca; Salvadori, Claudio; Petracca, Matteo; Pagano, Paolo; Saletti, Roberto

doi:10.1109/isie.2014.6864756

Cited by 8 publications

(5 citation statements)

References 8 publications

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“…A brief comparison of different approaches that imply computation of histograms is shown in Table 1. It can be noted how, as previously introduced, histograms are involved in different fields: the top part of the table refers to solutions for time domain experiments ( [32]- [35]), while the lower part features applications in the field of computer vision and image processing ( [11], [12], [36]- [38]). The implementation trend results in FPGAs as the dominating technology and strictly follows the field of application, making the listed solutions not very suitable for an easy cross-domain utilization, but rather for operating in the environment they were created for in the first place.…”

Section: Trend Of Implementation Strategy and State-of-the-artmentioning

confidence: 99%

“…Table 2 summarizes the most effective results in FPGA-based histogram modules, focusing on the FoMs presented. In [36], the pipeline composed of the memory and the increment mechanism has a duration of 4 clock cycles, with 2 additional cycles for the read-out, reaching a total pipeline of 6 clock cycles. Such a long pipeline makes it possible to split the combination block, in order to guarantee a low propagation delay, making it possible to work with a clock up to 100 MHz,with N = 8 and M = 32.…”

Section: Trend Of Implementation Strategy and State-of-the-artmentioning

confidence: 99%

“…LUTs and FFs values are, if not explicitly specified, derived and adapted to Xilinx 7 series equivalent (i.e. ''Logic Elements'' in[36] are traduced to Slices from Xilinx, each containing 4 LUTs and 8 FFs)…”

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confidence: 99%

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High-Performance Computing of Real-Time and Multichannel Histograms: A Full FPGA Approach

et al. 2022

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In a world heading towards applications, in science and industry, based on big data processing, the ability to elaborate streams of data is becoming more important every day. Applications of various natures, ranging from biology to chemistry, from medical imaging to spectroscopy, need systems able to detect, process and store huge amounts of data in real-time. In this context, techniques such as histogramming come into play. Histograms are able to represent data shapes and retrieve statistical information, favoring further processing. This kind of processing is usually done with the help of general purpose processors, relying on temporal computing, with their pros (simplicity and fast operating frequencies) and cons (inability to exploit parallel computation). Both Industry and Academia have, however, proposed many solutions to this need, delivering histogram generators both in full-custom Application-Specific Integrated Circuits (ASICs) and Field-Programmable Gate Array (FPGA) IP-Cores, preferred over processors thanks to their superior parallel computing power. In this work, we present a full FPGA approach to this issue, resulting in a high-performance IP-Core for generating and managing multiple histograms in real time, each supporting a data flow up to 224 MSps, with a strong focus on overall flexibility and area efficiency, using as low as < 250 LUTs and 300 FFs resources for a 16 bit-wide, 4096-bin histogram implementation. The IP-Core has been successfully integrated and validated in a high-performance time-mode application: an FPGA-based Time-to-Digital Converter. The resulting IP-Core is, more in general, a single solution perfectly adaptable to any field of application and FPGA device.INDEX TERMS Field-programmable gate array (FPGA), histograms, real-time systems, IP-Cores, throughput.

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Section: Trend Of Implementation Strategy and State-of-the-artmentioning

confidence: 99%

Section: Trend Of Implementation Strategy and State-of-the-artmentioning

confidence: 99%

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High-Performance Computing of Real-Time and Multichannel Histograms: A Full FPGA Approach

et al. 2022

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“…5. It is a modified version of one initially presented in [25] and uses two distinct histogram modules (SubCell0 and SubCell1 in Fig. 5).…”

Section: Histogram Computationmentioning

confidence: 99%

Bio-inspired heterogeneous architecture for real-time pedestrian detection applications

Maggiani

Bourrasset

Quinton

et al. 2016

J Real-Time Image Proc

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International audienceAlong with the development of powerful processing platforms, heterogeneous architectures are nowadays permitting new design space explorations. In this paper we propose a novel heterogeneous architecture for reliable pedestrian detection applications. It deploys an efficient Histogram of Oriented Gradient pipeline tightly coupled with a neuro-inspired spatio-temporal filter. By relying on hardware-software co-design principles, our architecture is capable of processing video sequences from real-word dynamic environments in real-time. The paper presents the implemented algorithm and details the proposed architecture for executing it, exposing in particular the partitioning decisions made to meet the required performance. A prototype implementation is described and the results obtained are discussed with respect to other state of the art solutions

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“…In this Section, our HOG-Dot method is then compared with the state of the art HOG implementation. In order to compare the results, an entire hardware HOG pipeline has been deployed following the module presented in [13]. The HOG-Dot hardware module is then followed by the histogram circuit which provides to the classifier an ordered flow of oriented gradient over 8 × 8 pixel cells.…”

Section: Performance Evaluationmentioning

confidence: 99%

Parallel image gradient extraction core for FPGA-based smart cameras

Maggiani¹,

Bourrasset

Berry

et al. 2015

Proceedings of the 9th International Conference on Distributed Smart Cameras

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One of the biggest efforts in designing pervasive Smart Camera Networks (SCNs) is the implementation of complex and computationally intensive computer vision algorithms on resource constrained embedded devices. For low-level processing FPGA devices are excellent candidates because they support massive and fine grain data parallelism with high data throughput. However, if FPGAs offers a way to meet the stringent constraints of real-time execution, their exploitation often require significant algorithmic reformulations. In this paper, we propose a reformulation of a kernel-based gradient computation module specially suited to FPGA implementations. This resulting algorithm operates on-the-fly, without the need of video buffers and delivers a constant throughput. It has been tested and used as the first stage of an application performing extraction of Histograms of Oriented Gradients (HOG). Evaluation shows that its performance and low memory requirement perfectly matches low cost and memory constrained embedded devices.

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Reconfigurable architecture for computing histograms in real-time tailored to FPGA-based smart camera

Cited by 8 publications

References 8 publications

High-Performance Computing of Real-Time and Multichannel Histograms: A Full FPGA Approach

High-Performance Computing of Real-Time and Multichannel Histograms: A Full FPGA Approach

Bio-inspired heterogeneous architecture for real-time pedestrian detection applications

Parallel image gradient extraction core for FPGA-based smart cameras

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