Reconfigurable Architecture for Noise Cancellation in Acoustic Environment Using Single Multiply Accumulate Adaline Filter

Ezilarasan, M. R.; Pari, Jyothish; Leung, Man-Fai

doi:10.3390/electronics12040810

Cited by 9 publications

(4 citation statements)

References 19 publications

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“…The effects of long-term sickness from post-traumatic stress disorder are linked to severe pain, disability, and social/emotional impairment. A unique kind of ANN that can be employed for noise cancellation in an auditory environment is constructed in FPGA [17]. In this procedure, an adaptive filter is used after the ICA.…”

Section: Related Workmentioning

confidence: 99%

An Efficient EEG Signal Analysis for Emotion Recognition Using FPGA

Ezilarasan,

Leung

2024

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Electroencephalography (EEG), electromyography (EMG), galvanic skin response (GSR), and electrocardiogram (ECG) are among the techniques developed for collecting psychophysiological data from humans. This study presents a feature extraction technique for identifying emotions in EEG-based data from the human brain. Independent component analysis (ICA) was employed to eliminate artifacts from the raw brain signals before applying signal extraction to a convolutional neural network (CNN) for emotion identification. These features were then learned by the proposed CNN-LSTM (long short-term memory) algorithm, which includes a ResNet-152 classifier. The CNN-LSTM with ResNet-152 algorithm was used for the accurate detection and analysis of human emotional data. The SEED V dataset was employed for data collection in this study, and the implementation was carried out using an Altera DE2 FPGA development board, demonstrating improved performance in terms of FPGA speed and area optimization.

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Section: Related Workmentioning

confidence: 99%

An Efficient EEG Signal Analysis for Emotion Recognition Using FPGA

Ezilarasan,

Leung

2024

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“…This design also can achieve a very high degree of parallelism, because the PEs are computing the MACs simultaneously. The separate MAC unit design is currently used in various FPGA designs, such as CNN accelerators [10,13], and hardware implementation of other algorithms [24].…”

Section: Conventional Accelerator Design For Convmentioning

confidence: 99%

Design of a Generic Dynamically Reconfigurable Convolutional Neural Network Accelerator with Optimal Balance

Tong,

Han,

Han

et al. 2024

Electronics

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In many scenarios, edge devices perform computations for applications such as target detection and tracking, multimodal sensor fusion, low-light image enhancement, and image segmentation. There is an increasing trend of deploying and running multiple different network models on one hardware platform, but there is a lack of generic acceleration architectures that support standard convolution (CONV), depthwise separable CONV, and deconvolution (DeCONV) layers in such complex scenarios. In response, this paper proposes a more versatile dynamically reconfigurable CNN accelerator with a highly unified computing scheme. The proposed design, which is compatible with standard CNNs, lightweight CNNs, and CNNs with DeCONV layers, further improves the resource utilization and reduces the gap of efficiency when deploying different models. Thus, the hardware balance during the alternating execution of multiple models is enhanced. Compared to a state-of-the-art CNN accelerator, Xilinx DPU B4096, our optimized architecture achieves resource utilization improvements of 1.08× for VGG16 and 1.77× for MobileNetV1 in inference tasks on the Xilinx ZCU102 platform. The resource utilization and efficiency degradation between these two models are reduced to 59.6% and 63.7%, respectively. Furthermore, the proposed architecture can properly run DeCONV layers and demonstrates good performance.

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“…In both cases, the amount of digitized data to be transferred to the computer can become a bottleneck when the number of channels and count rates in the detectors are large. As an alternative, the required calculations for the DPSA can be performed with reduced latencies by utilizing field-programmable gate arrays (FPGAs) and hardware process acceleration techniques, which are extensively used (see [5]). This potentially enables real-time applications such as time-of-flight (ToF) measurements related to the measurement of neutron spectra in various types of nuclear physics experiments, especially under high count rate conditions [6,7].…”

Section: Introductionmentioning

confidence: 99%

Hardware Acceleration of Digital Pulse Shape Analysis Using FPGAs

González,

Ruiz,

Carpeño

et al. 2024

Sensors

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The BC501A sensor is a liquid scintillator frequently used in nuclear physics for detecting fast neutrons. This paper describes a hardware implementation of digital pulse shape analysis (DPSA) for real-time analysis. DPSA is an algorithm that extracts the physically relevant parameters from the detected BC501A signals. The hardware solution is implemented in a MicroTCA system that provides the physical, mechanical, electrical, and cooling support for an AMC board (NAMC-ZYNQ-FMC) with a Xilinx ZYNQ Ultrascale-MP SoC. The Xilinx FPGA programmable logic implements a JESD204B interface to high-speed ADCs. The physical and datalink JESD204B layers are implemented using hardware description language (HDL), while the Xilinx high-level synthesis language (HLS) is used for the transport and application layers. The DPSA algorithm is a JESD204B application layer that includes a FIR filter and a constant fraction discriminator (CFD) function, a baseline calculation function, a peak detection function, and an energy calculation function. This architecture achieves an analysis mean time of less than 100 µs per signal with an FPGA resource utilization of about 50% of its most used resources. This paper presents a high-performance DPSA embedded system that interfaces with a 1 GS/s ADC and performs accurate calculations with relatively low latency.

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Reconfigurable Architecture for Noise Cancellation in Acoustic Environment Using Single Multiply Accumulate Adaline Filter

Cited by 9 publications

References 19 publications

An Efficient EEG Signal Analysis for Emotion Recognition Using FPGA

An Efficient EEG Signal Analysis for Emotion Recognition Using FPGA

Design of a Generic Dynamically Reconfigurable Convolutional Neural Network Accelerator with Optimal Balance

Hardware Acceleration of Digital Pulse Shape Analysis Using FPGAs

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