Reconfigurable Architecture for Ultrasonic Signal Compression and Target Detection

Abstract

In this paper, we present a reconfigurable ultrasonic processor which can simultaneously employ two different ultrasonic imaging applications: ultrasonic target detection and signal compression. The underlying hardware design makes use of the fact that both applications share the same algorithm fundamentals. A unified architecture implements signal decomposition and reconstruction with forward and inverse DCT and DWT transforms. After the forward transform step, a thresholding operation is applied to discriminate either frequency bands for target detection or coefficient amplitudes for data compression. The flexibility and the modular design make this reconfigurable architecture an effective and practical solution for real-time ultrasonic imaging applications.

Dynamically Reconfigurable Architecture Design for Ultrasonic Imaging

“…For hardware realization of ultrasonic detection and compression applications, we have designed a reconfigurable subband decomposition processor (RSDP) that can implement various wavelet kernels for subband decomposition of the ultrasonic data. An earlier version of the reconfigurable architecture was proposed in our earlier work [5]. In this paper, an improved architecture is presented with a case study using a field-programmable gate array (FPGA) implementation.…”