Reconfigurable Cache Implemented on an FPGA

Gil, Alain Manuel Chaple; Benítez, José Ignacio Benavides; Calvino, M. Hernandez; Gómez, Ezequiel Herruzo

doi:10.1109/reconfig.2010.26

Cited by 14 publications

(9 citation statements)

References 8 publications

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“…Compared to a conventional direct mapped cache, the average savings are more modest, but the direct mapped cache suffers large penalties for some examplesup to 284% for parser, with degraded performance in several examples. Santana Gil et al [5] proposed a design for reconfigurable cache with fixed size, the cache design can work as direct mapped cache or as 2 way set associative cache, and can select 1, 2, 4 or 8 words per block for each mode.…”

Section: Comprehensive Studiesmentioning

confidence: 99%

Comparative Study of Reconfigurable Cache Memory

Omran¹,

Amory²

2017

Cihan Univ.-Erbil Sci. J.

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Reconfigurable cache memory is important to improve the cache performance and reduces the energy consumption. In this paper, a review for previous papers related with reconfigurable cache memory were presented and compared it with our work in which we implemented two dimensional reconfigurable cache memory with exploitation of full amount of cache memory size with different organizations and compare the performance of different cache organizations.

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Section: Comprehensive Studiesmentioning

confidence: 99%

Comparative Study of Reconfigurable Cache Memory

Omran¹,

Amory²

2017

Cihan Univ.-Erbil Sci. J.

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“…Thus, their systems are only tailored at simulation. Only few research work [24,21,22,23] is devoted to the physical implementation of the proposed cache models. Zhang et al [24] proposed a reconfigurable cache architecture where the cache ways configuration could be tuned via the combination of configuration register and physical address bits.…”

Section: Related Workmentioning

confidence: 99%

“…In addition, the number of the allocated cache ways can only be configured to be a power of two, which prevents the efficient usage of the limited cache ways. Gil et al [21,22] presented one general-purpose reconfigurable cache design only for uni-processor systems to be implemented on FPGA. Besides, the proposed reconfigurable cache design [21,22] can only work as direct mapped cache or 2-way set associative cache.…”

Section: Related Workmentioning

confidence: 99%

“…In contrast, hardware-based approach usually assigns cache ways within each cache set to different partitions with minimal timing overhead. However, most of the hardware-based cache partitioning approaches in the literature can only be used in uni-processor systems [21,22,23] or cannot strictly guarantee the cache space isolation among realtime applications [24].…”

Section: Introductionmentioning

confidence: 99%

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Reconfigurable cache for real-time MPSoCs: Scheduling and implementation

Chen

Huang

et al. 2016

Microprocessors and Microsystems

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Shared cache in modern multi-core systems has been considered as one of the major factors that degrade system predictability and performance. How to manage the shared cache for real-time multi-core systems in order to optimize the system performance while guaranteeing the system predictability is an open issue. In this paper, we present a reconfigurable cache architecture which supports dynamic cache partitioning at hardware level and a framework that can exploit cache management for real-time MPSoCs. The proposed reconfigurable cache allows cores to dynamically allocate cache resource with minimal timing overhead while guaranteeing strict cache isolation among the real-time tasks. The cache management framework automatically determines time-triggered schedule and cache configuration for each task to minimize cache misses while guaranteeing the real-time constraints. We evaluate the proposed framework with respect to different numbers of cores and cache modules and prototype the constructed MPSoCs on FPGA. Our experiments show that, our automatic framework brings significant benefits over the state-of-the-art cache management strategies when testing 27 benchmark programs on the constructed MPSoCs.

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“…[20], [22]). However, the prior efforts only evaluated singleported caches in isolation; that is, outside of the parallel accelerator scenario and without a comprehensive multibenchmark study.…”

Section: A Memory Architecture In Fpga-based Computingmentioning

confidence: 99%

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems

Choi

Nam

Canis

et al. 2012

2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines

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Abstract-We describe new multi-ported cache designs suitable for use in FPGA-based processor/parallel-accelerator systems, and evaluate their impact on application performance and area. The baseline system comprises a MIPS soft processor and custom hardware accelerators with a shared memory architecture: on-FPGA L1 cache backed by off-chip DDR2 SDRAM. Within this general system model, we evaluate traditional cache design parameters (cache size, line size, associativity). In the parallel accelerator context, we examine the impact of the cache design and its interface. Specifically, we look at how the number of cache ports affects performance when multiple hardware accelerators operate (and access memory) in parallel, and evaluate two different hardware implementations of multi-ported caches using: 1) multi-pumping, and 2) a recently-published approach based on the concept of a livevalue table. Results show that application performance depends strongly on the cache interface and architecture: for a system with 6 accelerators, depending on the cache design, speedup swings from 0.73× to 6.14×, on average, relative to a baseline sequential system (with a single accelerator and a direct-mapped, 2KB cache with 32B lines). Considering both performance and area, the best architecture is found to be a 4-port multi-pump direct-mapped cache with a 16KB cache size and a 128B line size.

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Reconfigurable Cache Implemented on an FPGA

Cited by 14 publications

References 8 publications

Comparative Study of Reconfigurable Cache Memory

Comparative Study of Reconfigurable Cache Memory

Reconfigurable cache for real-time MPSoCs: Scheduling and implementation

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems

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