Reconfigurable Computing and Hardware Acceleration in Health Informatics

Chowdhury, Mehdi Hasan; Cheung, Ray C. C.

doi:10.1007/978-3-030-54932-9_9

Cited by 2 publications

(1 citation statement)

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“…To implement the proposed algorithm at the circuit level, we have incorporated a field programmable gate array (FPGA) to design the hardware and verify the algorithm. A field programmable gate array (FPGA) is an integrated circuit which can be reconfigured according to the users' requirements [19]. Besides, when it comes to the question of processing multiple signals at the same time, a FPGA performs notably faster due to its inherent capacity of parallel computation [20,21].…”

Section: Introductionmentioning

confidence: 99%

An FPGA-Based Neuron Activity Extraction Unit for a Wireless Neural Interface

et al. 2020

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As computational and functional brain model development are solely dependent upon the data acquired from the neural interface, this device plays a vital role in both prosthetic developments and neurological experiments. A wireless neural interface is preferred over a traditional wired one because it can maximize the comfort of the subject and ensure the freedom of movement while implemented. This paper describes the field programmable gate array (FPGA) prototype design of a low-power multichannel neuron activity extraction unit suitable for a wireless neural interface. To achieve the low-power requirement, we proposed a novel neural signal extraction algorithm which can provide an up to 6000X transmission rate reduction considering the input signal. Consequently, this technique offers at least 2X power reduction compared to the state-of-the-art systems. We implemented this scheme in Xilinx Zynq-7000 FPGA, which can be used as an intermediate transition towards the application specific integrated circuit (ASIC) design for on-chip neural signal processing. The proposed FPGA prototype offers reconfigurable computability, which means the model can be modified and verified according to prerequisites before the final ASIC design. This prototype consists of a signal filtering unit and a signal extraction unit which can be used either as stand-alone units or combined as a complete system. Our proposed scheme also provides a provision to work as a single-channel or a scalable multichannel interface based on user’s demands. We collected practical neural signals from rat brains and validated the efficacy of the implemented system using in-silico signal processing.

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Section: Introductionmentioning

confidence: 99%