Reconfigurable computing using content addressable memory for improved performance and resource usage

Abstract

Conventional FPGA architectures leverage on the spatial computing model where the design to be realized is represented in the form of multi-input single-output lookup tables (LUTs). However, such a model incorporates a reconfigurable interconnect network which leads to significant design overhead and poor scalability with process technology. In this paper, we propose a multi-cycle Memory Based Computational methodology that utilizes Content Addressable Memory (CAM) as the underlying reconfigurable fabric. The use of CAM in the proposed framework leads to significant reduction in memory requirement compared to LUT-based approach. Simulation results for standard benchmark circuits indicate that the proposed CAM based implementation improves the memory requirement significantly compared to its LUT counterpart, at the cost of little or no degradation in performance.

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

“…To mitigate the limitation imposed by programmable interconnects, the concept of PLA-based logic evaluation has been explored which can drastically reduce the memory requirements in a reconfigurable computing framework [1]. Specifically, this method has been applied in the context of memory-based computing (MBC), a mixed spatial/ temporal reconfigurable computing paradigm which uses memory for traditional data storage, as well as for computation using LUTs.…”

“…Both purely spatial reconfigurable computing platforms like field-programmable gate arrays (FPGAs) [1], [91], [92] as well as various temporal computing platforms [2], [88], [89] can leverage the unique properties of nanoscale CAM structures and their associative search capabilities. Compared to the implementation of standard island-style FPGA architecture using nanoscale devices, time-multiplexed memory-based computing that uses dense CAM structures to implement logic functions (in contrast with 1-D LUTs stored in SRAM arrays) can be more effective in preserving the high integration density of nanoscale memory and improving performance due to a large reduction in programmable interconnect resources [2], as shown in Fig.…”

“…The concept of inmemory computing has been proposed in numerous earlier works [8], [9] in the context of computing in the main memory. However, with the emergence of fast and reliable nonvolatile storage, recent in-memory compute architectures have targeted these NVM technologies [1], [2], [6]. The benefits of such architectures are particularly noteworthy for pattern recognition, data mining, and other analytics applications, which traditionally involve moving a large volume of data through the memory hierarchy.…”

“…COMs are used in a computer system when an input address is not available for information being searched/stored and/or when very-highspeed parallel searching is required. Conceptually, COMs perform the inverse function of traditional random access memory (RAM) [1], which makes such memories well suited for fast parallel search of all stored data and comparison with the provided input. This has resulted in their widespread use in many application domainsVfrom branch prediction tables or cache controllers in processors, to lookup tables in high-speed routersVall requiring content-based search of the memory.…”

Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM

“…Beyond that, RRAM gathered interest for several other applications such as neuromorphic systems [7], [8], content-addressable memories (CAM) and nonvolatile SRAM [9], [10]. CAM memory systems allow searching by content as opposed to searching by address [11], [12]. This approach avoids frequent and expensive memory accesses in applications where searching operations among a large amount of data are required, such as pattern recognition, routing tables and branch prediction in a processor [10].…”