Reconfigurable data flow engine for HEVC motion estimation

D'huys, Thomas; Momcilovic, Svetislav; Pratas, Frederico; Sousa, Leonel

doi:10.1109/icip.2014.7025244

Cited by 7 publications

(10 citation statements)

References 4 publications

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“…A first-order comparison of designs is given in Table 2; the most common proposals for full-search ME are usually a variation of the structure given in [12]. Less number of comparators in the design [30] is obvious as it has fewer kinds of supported PB types. The bandwidth decreases, and the area increases in proportion to A 2 , approximately.…”

Section: Resultsmentioning

confidence: 99%

“…The synthesis report shows that the design can operate with a maximum clock frequency of 84.96 MHz. Table 3 shows a comparison with [30] implemented in the same FPGA. There are three proposals in [30], namely H64 P2, H64 P4 and H64 P8, and the H64 P8 design has the best performance among them even though it does not fit in this Xilinx Virtex-5 FPGA.…”

Section: Fpga Synthesis Resultsmentioning

confidence: 99%

“…Table 3 shows a comparison with [30] implemented in the same FPGA. There are three proposals in [30], namely H64 P2, H64 P4 and H64 P8, and the H64 P8 design has the best performance among them even though it does not fit in this Xilinx Virtex-5 FPGA. Thus, our design is compared with the H64 P8 design of [30].…”

Section: Fpga Synthesis Resultsmentioning

confidence: 99%

“…There are three proposals in [30], namely H64 P2, H64 P4 and H64 P8, and the H64 P8 design has the best performance among them even though it does not fit in this Xilinx Virtex-5 FPGA. Thus, our design is compared with the H64 P8 design of [30]. A basic difference between our proposed architecture and [30] is that the latter saves all first SAD computation results in memory then reorganises using a transposer, and feed to SAD comparators and 4-1 adders for calculating other higher-level SADs in the quad-tree structure.…”

Section: Fpga Synthesis Resultsmentioning

confidence: 99%

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VLSI Architecture of Full‐Search Variable‐Block‐Size Motion Estimation for HEVC Video Encoding

Vayalil

Kong

2017

IET Circuits, Devices & Syst

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Motion estimation (ME) is the most computationally intensive task in video encoding. This study proposes a fullsearch variable-block-size ME for the high-efficiency video coding or H.265 specification. The proposed method reduces memory requirements to a large extent by following a Morton order for data reading and a sum of absolute differences reuse strategy. The data bandwidth demand is also diminished by broadcasting data into multiple processing elements. This ME accelerator supports variable-block-size prediction blocks ranging from 8 × 4 to 64 × 64, and is reconfigurable in various search ranges for a trade-off between performance and area. The proposed method for very-large-scale integration (VLSI) architecture is synthesized with 32 nm technology, and is capable of real-time encoding of ultra-high-definition (4K-UHD, at 30 Hz) video with a search range of 64 pixels in both horizontal and vertical directions, operating at a frequency of 282 MHz.

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Section: Resultsmentioning

confidence: 99%

Section: Fpga Synthesis Resultsmentioning

confidence: 99%

Section: Fpga Synthesis Resultsmentioning

confidence: 99%

Section: Fpga Synthesis Resultsmentioning

confidence: 99%

See 2 more Smart Citations

VLSI Architecture of Full‐Search Variable‐Block‐Size Motion Estimation for HEVC Video Encoding

Vayalil

Kong

2017

IET Circuits, Devices & Syst

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“…However many works have already been devoted to the implementation of critical processing blocks of H.265/HEVC since the technical content of HEVC was finalized at the beginning of 2013. Table 5 reports the characteristics of three relevant hardware implementations on Virtex FPGAs that can be used to process an early exploration of the acceleration potential with dynamic reconfiguration: a motion estimation engine [11] which is the most computational part of the encoding process, a high performance intra prediction hardware [21] and an accelerator supporting fast forward and inverse two-dimensional transforms [33]. All implementation and performance results come from Xilinx Virtex devices and have been extrapolated to comply with the same video resolution and a running frequency of 100MHz.…”

Section: H265/hevc Encodermentioning

confidence: 99%

FoRTReSS: a flow for design space exploration of partially reconfigurable systems

Duhem

Muller

Bonamy

et al. 2015

Des Autom Embed Syst

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International audienceIn this paper, we present a flow enabling design space exploration for partially reconfigurable systems with real-time constraints, called FoRTReSS. FoRTReSS allows estimating mixed hardware/software implementations of an application where the hardware design space, the floorplanning of reconfigurable regions placed on the FPGA, is automatically inferred from application resources information, interface constraints and the target device. Real-time constraints are verified by a highly configurable SystemC simulator, RecoSim, handling applications described as control data flow graphs (CDFGs). We demonstrate our approach on an H.264 video decoder and an H.265 encoder targeting the latest Zynq-7000 platforms from Xilinx, embedding a Cortex-A9 dual-core processor. We show that an hardware/software implementation of the H.264 decoder using both processor cores and slice decomposition is possible under real-time constraints, effectively achieving a framerate of 30 frames per second while reducing area requirements compared to a static implementation, using 54 % less slice resources and 44 % less BRAM resources. Additionally we report the ability of the methodology to address very early analysis from high level application specification on the example of an H.265 encoder

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