Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications

Battezzati, N.; Sterpone, Luca; Violante, M.

doi:10.1007/978-1-4419-7595-9

Cited by 33 publications

(10 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A SEU in the configuration memory of PIPs may cause several types of topological modifications [28] that manifest themselves as logical faults on the output wires of the affected switch box [1], namely: stuck-at-0 (stuck-at-1 ), when a wire is stuck at the 0 (1) logic value; bridge, when the values of two wires are exchanged; wired-AND (wired-OR), when the value of an output wire is the AND (OR) of the values of two input wires; and wired-MIX, when the values of two output wires B and D are mixed so that they keep their correct values if the values of the respective input wires are equal, otherwise they take the complementary values. When FPGAs are used in safety-critical applications, on-line testing is one of the methods that can be applied at run-time to detect SEUs, and possibly reconfigure the FPGA.…”

Section: Fault Tolerance For Systems With Multiple Faultsmentioning

confidence: 99%

Application of Model Checking to Fault Tolerance Analysis

Bernardeschi

Domenici

2019

From Software Engineering to Formal Methods and Tools, and Back

View full text Add to dashboard Cite

A basic concept in modeling fault tolerant systems is that anticipated faults, being obviously outside of our control, may or may not occur. A fault tolerant system design can be proved to correctly behave under a given fault hypothesis, by proving the observational equivalence between the system design specification and the fault-free system specification. Additionally, model checking of a temporal logic formula which gives an abstract notion of correct behavior can be applied to verify the correctness of the design. The usage of model checking and temporal logic gives additional opportunities to better analyze the system behavior in presence of faults.

show abstract

Section: Fault Tolerance For Systems With Multiple Faultsmentioning

confidence: 99%

Application of Model Checking to Fault Tolerance Analysis

Bernardeschi

Domenici

2019

From Software Engineering to Formal Methods and Tools, and Back

View full text Add to dashboard Cite

show abstract

“…There are three main sources of charged particles responsible for faults in electronic components, namely: Cosmic Rays, Solar Winds and Van Allen's Belt [50]. Cosmic Rays are formed of highly energetic ion nuclei, these heavy ions represent only 1% of the component of cosmic radiation, being the remaining 83% protons, 13% helium nuclei and 3% electrons [10].…”

Section: Radiation Effects On Electronicsmentioning

confidence: 99%

“…Errors caused by radiation, known as SEE, can be classified as soft-errors and hard-errors, and subdivided into the following [10]:…”

Section: Single Event Effectsmentioning

confidence: 99%

Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy

et al. 2019

View full text Add to dashboard Cite

Embedded soft-core processors are becoming the usual solution to deal with network and data communications inside FPGAs. However, when developing space-based applications, the designer must consider the effects of ionizing radiation such as Total Ionizing Dose (TID) and Single-Event Effect (SEE). The majority of techniques for mitigation of Single-Event Upsets (SEUs) on FPGAs are based on hardware spatial-redundancy. This work presents a fault-tolerance technique, based on the concept of temporal redundancy, with checkpoints and recovery for soft-core processors. The proposed modified architecture is aimed at embedded systems for space applications based on FPGAs. Our experimental results show that the Checkpoint Recovery technique is a valid alternative to traditional spatial-redundancy, especially when considering limited logic area and power budget present on a satellite. The results present levels of reliability comparable to those of the more conventional fault-tolerance techniques. Additionally, the proposed approach does not require modifications of the software source code or compiler.

show abstract

“…Every bit in the storage device requires one exclusive-OR (XOR) and one shift operation to the left by degree of a polynomial minus one bit [22].…”

Section:  mentioning

confidence: 99%

An Improved Frame Level Redundancy Scrubbing Algorithm for SRAM based FPGA

Haruna¹,

Abubilal²,

Salawudeen³

2017

IJCA

View full text Add to dashboard Cite

The use of Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) in critical applications has been considered a solution in space and avionics domain due to its flexibility in achieving multiple requirements such as re-programmability and good performance. However, SRAM-based FPGAs are susceptible to radiation induced Single Event Upset (SEU) that affects the functionality of the implemented design. Therefore, an improved Frame Level Redundancy (FLR) algorithm that uses Cyclic Redundancy Check (CRC) as an error detection technique for configuration memory scrubbing, is developed as a solution to mitigate SEU through upset detection and correction. Fault injection was performed on FPGA configuration memory frames on different number of modules to emulate SEU. The improved FLR algorithm was implemented and system level simulation was carried out using MATLAB. The performance of the improved FLR algorithm was compared with that of the existing FLR algorithm using error correction time and energy consumption as metrics. The results of this work showed that the improved FLR algorithm produced 31.6% improvement in error correction time and 61.1% improvement in energy consumption over the existing FLR algorithm.

show abstract

Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications

Cited by 33 publications

References 0 publications

Application of Model Checking to Fault Tolerance Analysis

Application of Model Checking to Fault Tolerance Analysis

Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy

An Improved Frame Level Redundancy Scrubbing Algorithm for SRAM based FPGA

Contact Info

Product

Resources

About