Reconfigurable Hardware Implementations of Tweakable Enciphering Schemes

Abstract

Abstract-Tweakable enciphering schemes are length-preserving block cipher modes of operation that provide a strong pseudorandom permutation. It has been suggested that these schemes can be used as the main building blocks for achieving in-place disk encryption. In the past few years, there has been an intense research activity toward constructing secure and efficient tweakable enciphering schemes. But actual experimental performance data of these newly proposed schemes are yet to be reported. In this paper, we present optimized FPGA implementations of six tweakable enciphering schemes, namely, HCH, HCTR, XCB, EME, HEH, and TET, using a 128-bit AES core as the underlying block cipher. We report the performance timings of these modes when using both pipelined and sequential AES structures. The universal polynomial hash function included in the specification of HCH, HCHfp (a variant of HCH), HCTR, XCB, TET, and HEH was implemented using a Karatsuba multiplier as the main building block. We provide detailed algorithm analysis of each of the schemes trying to exploit their inherent parallelism as much as possible. Our experiments show that a sequential AES core is not an attractive option for the design of these modes as it leads to rather poor throughput. In contrast, according to our place-and-route results on a Xilinx Virtex 4 FPGA, our designs achieve a throughput of 3.95 Gbps for HEH when using an encryption/decryption pipelined AES core, and a throughput of 5.71 Gbps for EME when using a encryption-only pipeline AES core. The performance results reported in this paper provide experimental evidence that hardware implementations of tweakable enciphering schemes can actually match and even outperform the data rates achieved by state-of-the-art disk controllers, thus showing that they might be used for achieving provably secure in-place hard disk encryption.

Efficient hardware implementations of brw polynomials and tweakable enciphering schemes

“…In those modes where both block-cipher and multiplier blocks were required, the critical path was decided by the later block. The obtained throughput figures were satisfactory with the design goal which was meant to match the speed of the modern day disk controllers (the interested reader can see [17] for a detailed discussion of the design decisions and the results obtained in that work). In [17], the constructions reported in [22] were not included as these constructions are more recent.…”

“…Almost all known TES schemes known before [22] were implemented in various hardware platforms in [17]. In [17], a careful analysis of the possible parallelism for all the modes was done and the designs tried to exploit the schemes' parallelism to their fullest extent.…”

“…In [17], a careful analysis of the possible parallelism for all the modes was done and the designs tried to exploit the schemes' parallelism to their fullest extent. The designs were targeted towards Virtex 4 family of FPGAs and the main design goal was speed.…”

A Modular Framework for Building Variable-Input-Length Tweakable Ciphers

“…Table 1 and Figure 2 compare existing algorithms with our new TCT 1 and TCT 2 constructions in terms of computational cost and security, respectively. Note that the finite field operations counted in Table 1 take hundreds of cycles in software [25,4], whereas their cost relative to an AES blockcipher invocation is much lower in hardware [26]. TCT 1 is the first tweakable cipher to require only a single blockcipher invocation and no extra finite field multiplications for each additional n bits of input, while TCT 2 is the first to provide beyond-birthday-bound security (and still gets away with a fixed number of finite field multiplications).…”

<monospace>STES</monospace>: A Stream Cipher Based Low Cost Scheme for Securing Stored Data

“…To our knowledge the only works which report implementations of TES in hardware are [15,31]. The designs in [31] are targeted towards the Xilinx Virtex 4 family of FPGAs while the designs in [15] were targeted towards the Virtex 5 family. The throughput reported in [15] is very encouraging as for all reported designs more than 10 Gbits/sec of throughput is obtained.…”