Reconfigurable Low Power Architecture for Fault Tolerant Pseudo-Random Number Generation

Abstract

High operating speed, fault tolerance (FT), low power and reconfiguration become today dominant issues during development and design of linear feedback shift registers (LFSRs), used as sequence generators, with randomness properties, in a process of testing complex CMOS VLSI ICs. In our design solution, we accomplish FT by using triple modular redundancy (TMR), i.e., a hardware scheme that uses spatial redundancy. For reduction of dynamic power consumption, clock-gating technique, as a simple and effective method, is implemented. The reconfigurable FPGA architecture provides us a feature to program and configure the degree of the primitive polynomial that the LFSR uses. High speed of operation, over 100 MHz, during testing is achieved by using circuits fabricated in submicron technology. An architecture which integrates in a single structure (IP core) all aforementioned design issues, named fault tolerant reconfigurable low-power pseudo-random number generator (FT_RLRG), is described in this article. The design of FT_RLRG is of practical interest in testing triple modular FT systems in the presence of single event upsets (SEUs), especially in a case when the design is SRAM-based. As an IP core the FT_RLRG has been implemented both on FPGA and ASIC technology. The main idea was to design a low-cost and low-power hardware structure which is able to adjust to any standards (past, present and future) operating at high-speed with different polynomials (currently up to 32nd order). The performance of FT_RLRG in respect to speed of operation (up to 150 MHz for FPGA and ASIC designs), low hardware overhead (0.033 mm2 area for ASIC and up to 530 slices for FPGA) and low-power consumption (0.45 mW for ASIC), for three different FPGA architecture (Spartan-3E, Virtex-4 and Virtex-6LP) and as an ASIC design implemented in 130 nm SiGe BiCMOS technology, have been estimated.