Reconfigurable on-chip interconnection networks for high performance embedded SoC design

Oveis-Gharan, Masoud; Khan, Gul N.

doi:10.1016/j.sysarc.2020.101711

Cited by 16 publications

(3 citation statements)

References 14 publications

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“…Due to its large bisection bandwidth, simple node connection, and low complexity routing algorithm, the mesh is the most popular topology. However, it is important to design a topology that adapts to applications requirements, i.e., an application-specific topology [ 36 , 37 ]. Dynamically reconfigurable hardware such as FPGA technology enables adaptable topology.…”

Section: The Motivation For An Sdnoc Approachmentioning

confidence: 99%

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

et al. 2021

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Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

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Section: The Motivation For An Sdnoc Approachmentioning

confidence: 99%

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

et al. 2021

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“…In the 2D mesh reconfigurable on-chip network detailed by Oveis et al, comprising communication and router layers, scalability and fault tolerance were limited despite the ability to reconstruct different topological forms [6]. Congestion diversion and obstacle avoidance remain unaddressed.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Reconfigurable Array Adaptive Optoelectronic Hybrid Interconnect Shunting Network

Yang,

Li,

et al. 2024

Electronics

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Addressing challenges regarding Hybrid Optoelectronic Network-on-Chip systems, such as congestion control, their limited adaptability, and their inability to facilitate optoelectronic co-simulation, this study introduces an adaptive hybrid optoelectronic interconnection shunt structure tailored for reconfigurable array processors. Within this framework, an adaptive shunt routing algorithm and a low-loss non-blocking five-port optical router are developed. Furthermore, an adaptive hybrid optoelectronic interconnection simulation model and a performance statistical model, established using SystemVerilog and Verilog, complement these designs. The experimental results showcase promising enhancements: the designed routing algorithm demonstrates an average 17.5% improvement in mitigating congestion at network edge nodes; substantial reductions in the required number of cross waveguides and micro-ring resonators for optical routers lead to an average path insertion loss of only 0.522 dB. Moreover, the hybrid optoelectronic interconnection performance statistical model supports the design of routing strategies and topology structures, enabling resource usage, power consumption, insertion loss, and other performance metrics to be accurately assessed.

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“…Researchers in [4][5][6][7] have proposed run-time reconfigurable topologies to introduce dynamic flexibility to communication needs. Different adaptive routing algorithms have been proposed in [8][9][10][11][12][13][14] for dynamically reconfigurable NoCs that are capable of avoiding deadlock and obstacles by bypassing faulty components. The functional examples [15] of FPGA partial reconfiguration and the accompanying design tools are in abundance.…”

Section: Introductionmentioning

confidence: 99%

Dynamically Scalable NoC Architecture for Implementing Run-Time Reconfigurable Applications

Ijaz,

Kidane,

Bourennane

et al. 2023

Micromachines

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The paper proposes two architectures for a dynamically scalable network-on-chip (NoC) for dynamically reconfigurable intellectual properties (IPs) to save power. The first architecture is a run-time scalable column-based NoC, where the columns of the NoC are scaled up and down at run-time depending on the demands to connect reconfigurable IPs. The second architecture is an extension of the first, where both the rows and columns of the NoC are dynamically scaled up and down on demand. A robust control manager is developed to control the IP and sub-NoC reconfigurations by optimizing the reconfiguration costs. The proposed architectures have been implemented and tested in actual prototypes on a Virtex 6 FPGA mounted on the ML605 board. The results show that dynamically scalable architectures are capable of significant power reduction as compared to traditional static architectures for the same size of the NoC. It is anticipated that the scalable NoC can be very useful for sharing the FPGA resources among IPs at runtime.

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Reconfigurable on-chip interconnection networks for high performance embedded SoC design

Cited by 16 publications

References 14 publications

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Design and Implementation of Reconfigurable Array Adaptive Optoelectronic Hybrid Interconnect Shunting Network

Dynamically Scalable NoC Architecture for Implementing Run-Time Reconfigurable Applications

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