Reconfigurable signal processor for channel coding and decoding in low SNR wireless communications

Halter, S.; Oberg, M.; Chau, P.M.; Siegel, Paul H.

doi:10.1109/sips.1998.715789

Cited by 13 publications

(6 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As a consequence, there is a potential net area decrease of 30 %, provided the specific decoder implementation can exploit the module reuse. For example, the traditional complete or partial loop unfolding resulting in a serial module setup [1] [4][5] offers this possibility.…”

Section: Tradeoff Analysis and Simulation Resultsmentioning

confidence: 99%

“…To remedy this, we have carried out a systemic exploration [10]. Although the basic methodology is equally applicable to both classes, we have focussed on MAP algorithms since they offer a superior decoding performance [11] and have an implementation cost that is comparable to that of SOVA when using sliding windows [4]. At the end of our systemic memory optimizations, however, we can not present one optimal structure to the designer.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Memory optimization of MAP turbo decoder algorithms

Schurgers

Catthoor

Engels

2001

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Turbo codes are the most recent breakthrough in coding theory. However, the decoder's implementation cost limits their incorporation in commercial systems. Although the decoding algorithm is highly data dominated, no true memory optimization study has been performed yet. We have extensively and systematically investigated different memory optimizations for the MAP (Maximum A Posteriori) class of decoding algorithms. It turns out that it is not possible to present one decoder structure as being optimal. In fact, there are several tradeoffs, which depend on the specific turbo code, the implementation target (hardware or software), and the selected cost function. We therefore end up with a parametric family of new optimized algorithms out of which the designer can choose. The impact of our optimizations is illustrated by a representative example, which shows a significant decrease in both decoding energy (factor 2.5) and delay (factor 1.7).

show abstract

Section: Tradeoff Analysis and Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Memory optimization of MAP turbo decoder algorithms

Schurgers

Catthoor

Engels

2001

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…The use of sliding windows has been proposed as a very powerful technique to limit the amount of memory storage that is required for the MAX-LOG-MAP algorithm and other classes of MAP decoding [10,17]. The main idea is to start the backward recursions not at the end of the block, but at some other point k where the metrics are initialized with equal values for each state.…”

Section: Sliding Windowsmentioning

confidence: 99%

“…Some of the most powerful ones are shifting the calculations to the logarithmic domain [7,11,21] and the introduction of sliding windows [10,15,17,22,28]. A stop criterion terminates the iterative decoding process thereby significantly cutting down on unnecessary iteration steps [3,4,15].…”

Section: Related Workmentioning

confidence: 99%

“…A vast number of techniques have been proposed over the years to tackle this issue. These range from memory optimizations [9,20], to architectural variants [6,15,17] and computational simplifications [3,4,14]. Since turbo coding draws its appeal from a supreme coding efficiency, it is crucial that modifications for the sake of improving implementation complexity due not sacrifice decoding performance.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Traceback-Based Optimizations for Maximum a Posteriori Decoding Algorithms

Schurgers

Chandrakasan

2008

J Sign Process Syst Sign Image Video Technol

View full text Add to dashboard Cite

Maximum A Posteriori (MAP) decoding is a crucial enabler of turbo coding and other powerful feedbackbased algorithms. To allow pervasive use of these techniques in resources constrained systems, it is important to limit their implementation complexity, without sacrificing the superior performance they are known for. We show that introducing traceback information into the MAP algorithm, thereby leveraging components that are also part of Soft-Output Viterbi Algorithms (SOVA), offers two unique possibilities to simplify the computational requirements. Our proposed enhancements are effective at each individual decoding iteration and therefore provide gains on top of existing techniques such as early termination and memory optimizations. Based on these enhancements, we will present three new architectural variants for the decoder. Each one of these may be preferable depending on the decoder memory hardware requirements and number of trellis states. Computational complexity is reduced significantly, without incurring significant performance penalty.

show abstract