Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Multicore Architectures

Abstract

On-chip communication is widely considered to be one of the major performance bottlenecks in contemporary chip multiprocessors (CMPs). With recent advances in silicon nanophotonics, photonicbased networks-on-chip (NoCs) are being considered as a viable option for communication in emerging CMPs as they can enable higher bandwidth and lower power dissipation compared to traditional electrical NoCs. In this paper, we present UltraNoC, a novel reconfigurable silicon-photonic NoC architecture that features improved channel sharing and supports dynamic re-prioritization and exchange of bandwidth between clusters of cores running multiple applications, to increase channel utilization and performance. Experimental results show that UltraNoC improves throughput by up to 9.8× while reducing latency by up to 55% and energy-delay product by up to 90% over state-of-the-art solutions.

SWIFTNoC

“…To evaluate our proposed SwiftNoC architecture, we compared it to a traditional electrical mesh (EMesh) based NoC as well as to four state-of-the-art photonic crossbar NoCs: UltraNoC with concurrent token stream arbitration [Chittamuru et al 2015], Flexishare with token stream arbitration [Pan et al 2010], Firefly with reservationassisted single-write-multiple-reader (R-SWMR) data waveguides [Pan et al 2009], and Corona with an enhanced token-slot arbitration [Vantrease et al 2009]. We modeled and simulated the architectures at a cycle-accurate granularity with a SystemCbased NoC simulator for two CMP platform complexities: 64 core and 256 core.…”

“…A limitation of this approach is that a fixed time gap is required between two arbitration slots to set up data for transmission, which reduces the available time slots to send data. UltraNoC [Chittamuru et al 2015] improves on these prior works by utilizing a more effective concurrent token stream arbitration strategy, together with support for reconfigurable cluster prioritization and bandwidth re-allocation to improve MWMR photonic channel utilization.…”

“…The baseline UltraNoC architecture [Chittamuru et al 2015] is designed for a 64-core CMP, as shown in Figure 1. We also extend the baseline architecture to a 256-core CMP for the purposes of scalability analysis.…”

Process variation aware crosstalk mitigation for DWDM based photonic NoC architectures

“…Several crossbar topology based PNoC architectures have been proposed to date (e.g., [4]- [6]). These architectures are built using silicon photonic devices such as microring-resonators (MRs) and silicon waveguides, and employ dense-wavelengthdivision-multiplexing (DWDM), where a large number of wavelengths are multiplexed in a waveguide to enable high bandwidth parallel data transfers.…”

Pico

“…Recent developments in the area of silicon photonics have enabled the integration of photonic components with CMOS circuits on a chip. Several photonic network-on-chip (PNoC) architectures have been proposed to date (e.g., [1]- [3]). These architectures employ onchip photonic links that use microring resonator (MR) modulators to modulate electrical signals onto photonic signals that travel through a silicon waveguide, and MR filter receivers that detect and drop photonic signals on to a photodetector to recover an electrical signal.…”