Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems

Abstract

A reconfigurable and programmable streaming processor core complemented with interconnected arithmetic units for the acceleration of floating-point operations is presented in this paper. The streaming processor can be easily reconfigured to perform a complex scientific algorithm or computations by changing the set of instructions in a central control unit. By using floating-point arithmetic unit with pipeline streaming data flow, floating-point operations can be performed in each cycle resulting in a high-performance scientific computations. The streaming processor is dedicated for a high-performance adaptive signal processing applications. For higher performance, reliability and fault-tolerance scientific computations, the streaming processor would be designed as a tile processor in a multicore streaming processor system. I. INTRODUCTIONStreaming processors are commonly used to accelerate the computations of a scientific formulas used in many engineering and information technology application areas. The scientific computations are specifically required to solve some chemical and physical problems, signal and image processing problems and other problems in civil and mechanical engineering. The scientific computations are often very complex and sometimes also require very short time constraints. By using a general-purpose computer system, the problem can be solved well functionally. However, due to the complexity of the scientific computations, high-performance requirements of the computation cannot be meet. Therefore, a specific streaming processor is proposed to solve the hard time constraint problem.Streaming processors have been widely developed for many applications. Some of them are implemented for example as an application-specific streaming processor. A few application examples can be found such as streaming processors for fluid dynamic computations based on lattice Boltzmann method [16] and for accelerating ray tracing traversal algorithm in a graphic rendering application [19]. The streaming processor can also be implemented as a reconfigurable streaming processor that can be reconfigured for several scientific computing applications. The RSVP TM streaming processor presented in [2] can be programmed by describing the shape and the location of vector data streams in memory and describing the computation of the streaming data in a data-flow graphs. However, the RSVP TM streaming processor does not support floating-pointbased arithmetic operations.A few floating-point-based processors that also support streaming computations have been developed so far. Intel Corporation has designed a 6.2-GFlops Floating-Point MultiplyAccumulator (FPMAC) [22]. The FPMAC processors are dedicated for a Teraflops Multicore System, which could run tera floating-point operations per second by interconnecting