Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices

Shrestha, Rahul; Sharma, Ashutosh

doi:10.1007/978-981-13-5950-7_4

Communications in Computer and Information Science

2019

DOI: 10.1007/978-981-13-5950-7_4

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Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices

Rahul Shrestha

Ashutosh Sharma

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Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices

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